A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. - Hao-I Yang; Shih-Chi Yang; Mao-Chih Hsia; Yung-Wei Lin; Yi-Wei Lin; Chien-Hen Chen; Chi-Shin Chang; Geng-Cing Lin; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; et al. (SoCC, 2011)

A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. - Yung-Wei Lin; Hao-I Yang; Mao-Chih Hsia; Yi-Wei Lin; Chien-Hen Chen; Ching-Te Chuang; Wei Hwang; Nan-Chun Lien; Kuen-Di Lee; Wei-Chiang Shih; Ya-Ping Wu; Wen-Ta Lee; et al. (SoCC, 2012)

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. - Chi-Shin Chang; Hao-I Yang; Wei-Nan Liao; Yi-Wei Lin; Nan-Chun Lien; Chien-Hen Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Ming-Hsien Tu; Huan-Shun Huang; Yong-Jyun Hu; et al. (ISCAS, 2013)

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. - Nan-Chun Lien; Li-Wei Chu; Chien-Hen Chen; Hao-I Yang; Ming-Hsien Tu; Paul-Sen Kan; Yong-Jyun Hu; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

An Open-source Framework for Autonomous SoC Design with Analog Block Generation. - Tutu Ajayi; Sumanth Kamineni; Yaswanth K. Cherivirala; Morteza Fayazi; Kyumin Kwon; Mehdi Saligane; Shourya Gupta; Chien-Hen Chen; Dennis Sylvester; David T. Blaauw; Ronald G. Dreslinski; Benton H. Calhoun; et al. (VLSI-SOC, 2020)

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation. - Tutu Ajayi; Sumanth Kamineni; Morteza Fayazi; Yaswanth K. Cherivirala; Kyumin Kwon; Shourya Gupta; Wenbo Duan; Jeongsup Lee; Chien-Hen Chen; Mehdi Saligane; Dennis Sylvester; David T. Blaauw; et al. (VLSI-SoC (Selected Papers), 2020)