Chien-Hsing Wu

According to our database, Chien-Hsing Wu authored at least 16 papers between 1995 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Robust Training Symbol Assisted Least Squares Estimation for Direct Conversion Receivers with Oscillator IQ-Imbalance.

Chia-Peng Chou, Tsung-Hsien Liu, Chien-Hsing Wu

Wirel. Pers. Commun., 2017

2009

Space-Frequency-Coded MIMO OFDM Receivers Based on Gaussian Message Passing.

Chia-Peng Chou, Chien-Hsing Wu, Tsung-Hsien Liu, Yin-Tsung Hwang

Proceedings of IEEE International Conference on Communications, 2009

2005

VLSI architectural design tradeoffs for sliding-window log-MAP decoders.

Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen

IEEE Trans. Very Large Scale Integr. Syst., 2005

Quantum circuits for stabilizer codes.

Chien-Hsing Wu, Yan-Chr Tsai, Hwa-Long Tsai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m).

Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang

IEEE Trans. Computers, 2004

VLSI architecture exploration for sliding-window Log-MAP decoders.

Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

FPGA realization of an OFDM frame synchronization design for dispersive channels.

Yin-Tsung Hwang, Kuo-Wei Liao, Chien-Hsing Wu

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Novel Algorithms and VLSI Design for Division over GF(2^m).

Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

An area-efficient systolic division circuit over GF(2^m) for secure communication.

Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Memory arrangements in turbo decoders using sliding-window BCJR algorithm.

Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design.

Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

VLSI architecture of extended in-place path metric update for Viterbi decoders.

Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

An efficient approach for in-place scheduling of path metric update in Viterbi decoders.

Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem.

Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

An area-efficient versatile Reed-Solomon decoder for ADSL.

Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1995

Design of an MPEG-based set-top box for video on demand services.

Yin-Hwa Huang, Yuo-Chuan Chang, Chi-Shyan Wu, Chien-Hsing Wu

Proceedings of the 1995 International Conference on Acoustics, 1995