Design of an MPEG-based set-top box for video on demand services. - Yin-Hwa Huang; Yuo-Chuan Chang; Chi-Shyan Wu; Chien-Hsing Wu 002 (ICASSP, 1995)

An area-efficient versatile Reed-Solomon decoder for ADSL. - Jin-Chuan Huang; Chien-Ming Wu; Ming-Der Shieh; Chien-Hsing Wu 002 (ISCAS (1), 1999)

A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. - Che-Han Wu; Ming-Der Shieh; Chien-Hsing Wu 002; Ming-Hwa Sheu; Jia-Lin Sheu (ISCAS (1), 1999)

An efficient approach for in-place scheduling of path metric update in Viterbi decoders. - Chien-Ming Wu; Ming-Der Shieh; Chien-Hsing Wu 002; Ming-Hwa Sheu (ISCAS, 2000)

VLSI architecture of extended in-place path metric update for Viterbi decoders. - Chien-Ming Wu; Ming-Der Shieh; Chien-Hsing Wu 002; Ming-Hwa Sheu (ISCAS (4), 2001)

Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. - Chien-Hsing Wu 002; Chien-Ming Wu; Ming-Der Shieh; Yin-Tsung Hwang (ISCAS (4), 2001)

Memory arrangements in turbo decoders using sliding-window BCJR algorithm. - Chien-Ming Wu; Ming-Der Shieh; Chien-Hsing Wu 002 (ISCAS (5), 2002)

An area-efficient systolic division circuit over GF(2m) for secure communication. - Chien-Hsing Wu 002; Chien-Ming Wu; Ming-Der Shieh; Yin-Tsung Hwang (ISCAS (5), 2002)

Novel Algorithms and VLSI Design for Division over GF(2m). - Chien-Hsing Wu 002; Chien-Ming Wu; Ming-Der Shieh; Yin-Tsung Hwang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

FPGA realization of an OFDM frame synchronization design for dispersive channels. - Yin-Tsung Hwang; Kuo-Wei Liao; Chien-Hsing Wu 002 (ISCAS (2), 2003)

VLSI architecture exploration for sliding-window Log-MAP decoders. - Chien-Ming Wu; Ming-Der Shieh; Chien-Hsing Wu 002; Yin-Tsung Hwang; Jun-Hong Chen; Hsin-Fu Lo (ISCAS (2), 2004)

High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). - Chien-Hsing Wu 002; Chien-Ming Wu; Ming-Der Shieh; Yin-Tsung Hwang (IEEE Trans. Computers, 2004)

Quantum circuits for stabilizer codes. - Chien-Hsing Wu 002; Yan-Chr Tsai; Hwa-Long Tsai (ISCAS (3), 2005)

VLSI architectural design tradeoffs for sliding-window log-MAP decoders. - Chien-Ming Wu; Ming-Der Shieh; Chien-Hsing Wu 002; Yin-Tsung Hwang; Jun-Hong Chen (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Space-Frequency-Coded MIMO OFDM Receivers Based on Gaussian Message Passing. - Chia-Peng Chou; Chien-Hsing Wu 002; Tsung-Hsien Liu; Yin-Tsung Hwang (ICC, 2009)

Robust Training Symbol Assisted Least Squares Estimation for Direct Conversion Receivers with Oscillator IQ-Imbalance. - Chia-Peng Chou; Tsung-Hsien Liu; Chien-Hsing Wu 002 (Wirel. Pers. Commun., 2017)