A serial link transceiver for USB2 high-speed mode. - Shyh-Jye Jou; Shu-Hua Kuo; Jui-Ta Chiu; Chu King; Chien-Hsiung Lee; Tim Liu (ISCAS (4), 2001)

Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. - Jyh-Ting Lai; An-Yeu Wu; Chien-Hsiung Lee (IEEE Trans. Very Large Scale Integr. Syst., 2007)