A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC. - Chien-Jian Tseng; Hung-Wei Chen; Wei-Ting Shen; Wei-Chih Cheng; Hsin-Shu Chen (IEEE J. Solid State Circuits, 2012)

A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC. - Chien-Jian Tseng; Yi-Chun Hsieh; Ching-Hua Yang; Hsin-Shu Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration. - Chien-Jian Tseng; Chieh-Fan Lai; Hsin-Shu Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

LEGO: A 12nm FinFET Analog Cell Library for Analog/Mixed-Signal Applications. - Xindi Liu; Chien-Jian Tseng; Richard Shi (ACM Great Lakes Symposium on VLSI, 2025)