A 2×25 Gb/s clock and data recovery with background amplitude-locked loop. - Chien-Kai Kao; Kuan-Lin Fu; Shen-Iuan Liu (A-SSCC, 2014)

A 37.8dB Channel Loss 0.6μs Lock Time CDR with Flash Frequency Acquisition in 5nm FinFET. - Chien-Kai Kao; Shih-Che Hung; Tse-Hsien Yeh; Chen-Yu Hsiao (ISSCC, 2023)