Analysis of pattern-dependent and timing-dependent failures in an experimental test chip. - Jonathan T.-Y. Chang; Chao-Wen Tseng; Chien-Mo James Li; Mike Purtell; Edward J. McCluskey (ITC, 1998)

Testing for tunneling opens. - Chien-Mo James Li; Edward J. McCluskey (ITC, 2000)

Testing for resistive opens and stuck opens. - Chao-Wen Tseng; Chien-Mo James Li; Mike Purtell; Edward J. McCluskey (ITC, 2001)

Diagnosis of Tunneling Opens. - Chien-Mo James Li; Edward J. McCluskey (VTS, 2001)

Diagnosis of Sequence-Dependent Chips. - Chien-Mo James Li; Edward J. McCluskey (VTS, 2002)

ELF-Murphy Data on Defects and Test Sets. - Edward J. McCluskey; Ahmad A. Al-Yamani; Chien-Mo James Li; Chao-Wen Tseng; Erik H. Volkerink; François-Fabien Ferhani; Edward Li; Subhasish Mitra (VTS, 2004)

Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chains. - Hung-Mao Lin; James Chien-Mo Li (ITC, 2005)

Jump Scan: A DFT Technique for Low Power Testing. - Min-Hao Chiu; Chien-Mo James Li (VTS, 2005)

Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns. - James Chien-Mo Li (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains. - James Chien-Mo Li (IEEE Trans. Computers, 2005)

Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs. - Chien-Mo James Li; Edward J. McCluskey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Diagnosis of single stuck-at faults and multiple timing faults in scan chains. - James Chien-Mo Li (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis. - Yu-Long Kao; Wei-Shun Chuang; James Chien-Mo Li (ITC, 2006)

Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies. - Chun-Yi Lee; Hung-Mao Lin; Fang-Min Wang; James Chien-Mo Li (ASP-DAC, 2007)

Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing. - Chun-Yi Lee; James Chien-Mo Li (J. Low Power Electron., 2007)

Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis. - James Chien-Mo Li; Hung-Mao Lin; Fang-Min Wang (IEEE Trans. Computers, 2007)

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. - Shianling Wu; Laung-Terng Wang; Zhigang Jiang; Jiayong Song; Boryau Sheu; Xiaoqing Wen; Michael S. Hsiao; James Chien-Mo Li; Jiun-Lang Huang; Ravi Apte (DFT, 2008)

IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores. - Geng-Ming Chiu; James Chien-Mo Li (ITC, 2008)

Diagnosis of Logic-to-chain Bridging Faults. - Wei-Chih Liu; Wei-Lin Tsai; Hsiu-Ting Lin; James Chien-Mo Li (ITC, 2008)

Survey of Scan Chain Diagnosis. - Yu Huang 005; Ruifeng Guo; Wu-Tung Cheng; James Chien-Mo Li (IEEE Des. Test Comput., 2008)

Simultaneous capture and shift power reduction test pattern generator for scan testing. - H.-T. Lin; J. C.-M. Li (IET Comput. Digit. Tech., 2008)

A Two-level Simultaneous Test Data and Time Reduction Technique for SOC. - Yu-Te Liaw; Bing-Chuan Bai; James Chien-Mo Li (J. Inf. Sci. Eng., 2008)

Diagnosis of Multiple Scan Chain Timing Faults. - Wei-Shun Chuang; Shiu-Ting Lin; Wei-Chih Liu; James Chien-Mo Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Effective and Economic Phase Noise Testing for Single-Chip TV Tuners. - James Chien-Mo Li; Po-Chou Lin; Chih-Ming Chiang; Chuo-Jan Pan; Chao-Wen Tseng (IEEE Trans. Instrum. Meas., 2008)

Fault modeling and testing of retention flip-flops in low power designs. - Bing-Chuan Bai; Augusli Kifli; Chien-Mo James Li; Kun-Cheng Wu (ASP-DAC, 2009)

Bridging Fault Diagnosis to Identify the Layer of Systematic Defects. - Po-Juei Chen; James Chien-Mo Li; Hsing Jasmine Chao (Asian Test Symposium, 2009)

Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits. - Shiue-Tsung Shen; Wei-Hsiao Liu; En-Hua Ma; James Chien-Mo Li; I-Chun Cheng (Asian Test Symposium, 2009)

BIST design optimization for large-scale embedded memory cores. - Tzuo-Fan Chien; Wen-Chi Chao; James Chien-Mo Li; Yao-Wen Chang; Kuan-Yu Liao; Ming-Tung Chang; Min-Hsiu Tsai; Chih-Mou Tseng (ICCAD, 2009)

Power scan: DFT for power switches in VLSI designs. - Bing-Chuan Bai; Chien-Mo James Li; Augusli Kifli; Even Tsai; Kun-Cheng Wu (ITC, 2009)

Very-Low-Voltage testing of amorphous silicon TFT circuits. - Shiue-Tsung Shen; Wei-Hsiao Liu; Chien-Mo James Li; I-Chun Cheng (ITC, 2009)

Time-space test response compaction and diagnosis based on BCH codes. - F.-M. Wang; W.-C. Wang; James Chien-Mo Li (IET Comput. Digit. Tech., 2009)

Static timing analysis for flexible TFT circuits. - Chao-Hsuan Hsu; Chester Liu; En-Hua Ma; James Chien-Mo Li (DAC, 2010)

CSER: BISER-based concurrent soft-error resilience. - Laung-Terng Wang; Nur A. Touba; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; James Chien-Mo Li (VTS, 2010)

DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In. - Wei-Chung Kao; Wei-Shun Chuang; Shiu-Ting Lin; Chien-Mo James Li; Vasco Manquinho (IEEE Trans. Very Large Scale Integr. Syst., 2010)

An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects. - Po-Juei Chen; Wei-Li Hsu; James Chien-Mo Li; Nan-Hsin Tseng; Kuo-Yin Chen; Wei-pin Changchien; Charles C. C. Liu (Asian Test Symposium, 2011)

An at-speed self-testable technique for the high speed domino adder. - Yu-Shun Wang; Min-Han Hsieh; Chia-Ming Liu; Chi-Wei Liu; James Chien-Mo Li; Charlie Chung-Ping Chen (CICC, 2011)

Test clock domain optimization for peak power supply noise reduction during scan. - Jen-Yang Wen; Yu-Chuan Huang; Min-Hong Tsai; Kuan-Yu Liao; James Chien-Mo Li; Ming-Tung Chang; Min-Hsiu Tsai; Chih-Mou Tseng; Hung-Chun Li (ITC, 2011)

Placement Optimization of Flexible TFT Digital Circuits. - Chester Liu; En-Hua Ma; Wen-En Wei; Chien-Mo James Li; I-Chun Cheng; Yung-Hui Yeh (IEEE Des. Test Comput., 2011)

An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology. - Chi-Hsuan Cheng; James Chien-Mo Li (J. Electron. Test., 2011)

Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips. - W.-C. Wang; C.-Y. Hsu; James Chien-Mo Li; Y.-C. Sung; A. Rao; L.-T. Wang (IET Comput. Digit. Tech., 2011)

A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives. - Kuan-Yu Liao; Chia-Yuan Chang; James Chien-Mo Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. - Shianling Wu; Laung-Terng Wang; Xiaoqing Wen; Zhigang Jiang; Lang Tan; Yu Zhang; Yu Hu 001; Wen-Ben Jone; Michael S. Hsiao; James Chien-Mo Li; Jiun-Lang Huang; Lizhen Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

3D IC test scheduling using simulated annealing. - Chih-Yao Hsu; Chun-Yi Kuo; James Chien-Mo Li; Krishnendu Chakrabarty (VLSI-DAT, 2012)

Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis. - Wei-Lin Tsai; Wei-Chih Liu; James Chien-Mo Li (IEEE Trans. Computers, 2012)

An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example. - Yu-Shun Wang; Min-Han Hsieh; James Chien-Mo Li; Charlie Chung-Ping Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. - Shianling Wu; Laung-Terng Wang; Xiaoqing Wen; Wen-Ben Jone; Michael S. Hsiao; Fangfang Li; James Chien-Mo Li; Jiun-Lang Huang (ACM Trans. Design Autom. Electr. Syst., 2012)

A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores. - Geng-Ming Chiu; James Chien-Mo Li (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM. - Bing-Chuan Bai; Chun-Lung Hsu; Ming-Hsueh Wu; Chen-An Chen; Yee-Wen Chen; Kun-Lun Luo; Liang-Chia Cheng; James Chien-Mo Li (Asian Test Symposium, 2013)

Test Generation of Path Delay Faults Induced by Defects in Power TSV. - Chi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; Krishnendu Chakrabarty (Asian Test Symposium, 2013)

GPU-based n-detect transition fault ATPG. - Kuan-Yu Liao; Sheng-Chang Hsu; James Chien-Mo Li (DAC, 2013)

Automatic test pattern generation for delay defects using timed characteristic functions. - Shin-Yann Ho; Shuo-Ren Lin; Ko-Lung Yuan; Chien-Yen Kuo; Kuan-Yu Liao; Jie-Hong R. Jiang; Chien-Mo James Li (ICCAD, 2013)

Compact Test Pattern Selection for Small Delay Defect. - Chia-Yuan Chang; Kuan-Yu Liao; Sheng-Chang Hsu; James Chien-Mo Li; Jiann-Chyi Rau (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

GPU-based timing-aware test generation for small delay defects. - Kuan-Yu Liao; Po-Juei Chen; Ang-Feng Lin; James Chien-Mo Li; Michael S. Hsiao; Laung-Terng Wang (ETS, 2014)

Divide and conquer diagnosis for multiple defects. - Shih-Min Chao; Po-Juei Chen; Jing-Yu Chen; Po-Hao Chen; Ang-Feng Lin; James Chien-Mo Li; Pei-Ying Hsueh; Chun-Yi Kuo; Ying-Yen Chen; Jih-Nung Li (ITC, 2014)

Physical-aware systematic multiple defect diagnosis. - Po-Juei Chen; Chieh-Chih Che; J. C.-M. Li; Shuo-Fen Kuo; Pei-Ying Hsueh; Chun-Yi Kuo; Jih-Nung Lee (IET Comput. Digit. Tech., 2014)

Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics. - Yen-Lung Chen; Wan-Rong Wu; Chien-Nan Jimmy Liu; James Chien-Mo Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits. - Chun-Yi Kuo; Chi-Jih Shih; Yi-Chang Lu; James Chien-Mo Li; Krishnendu Chakrabarty (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk. - Ming-Hong Tsai; Wei-Sheng Ding; Hung-Yi Hsieh; James Chien-Mo Li (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits. - Kuan-Ying Chiang; Yu-Hao Ho; Yo-Wei Chen; Cheng-Sheng Pan; James Chien-Mo Li (ATS, 2015)

TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects. - Ang-Feng Lin; Kuan-Yu Liao; Kuan-Ying Chiang; James Chien-Mo Li (VLSI-DAT, 2015)

Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration. - Cheng-Yu Han; Yu-Ching Li; Hao-Tien Kan; James Chien-Mo Li (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse. - Hung-I Lee; Chen-Yo Han; James Chien-Mo Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Test Pattern Modification for Average IR-Drop Reduction. - Wei-Sheng Ding; Hung-Yi Hsieh; Cheng-Yu Han; James Chien-Mo Li; Xiaoqing Wen (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Test Pattern Compression for Probabilistic Circuits. - Chih-Ming Chang; Kai-Jie Yang; James Chien-Mo Li; Hung Chen (ATS, 2017)

Test Methodology for Dual-rail Asynchronous Circuits. - Kuan-Yen Huang; Ting-Yu Shen; Chien-Mo James Li (DAC, 2017)

Physical-aware diagnosis of multiple interconnect defects. - Po-Hao Chen; Chi-Lin Lee; Jing-Yu Chen; Po-Wei Chen; James Chien-Mo Li (ITC-Asia, 2017)

Robust test pattern generation for hold-time faults in nanometer technologies. - Yu-Hao Ho; Yo-Wei Chen; Chih-Ming Chang; Kai-Chieh Yang; James Chien-Mo Li (VLSI-DAT, 2017)

PSN-aware circuit test timing prediction using machine learning. - Yu-Cheng Liu; Cheng-Yu Han; Shih-Ya Lin; James Chien-Mo Li (IET Comput. Digit. Tech., 2017)

Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. - Run-Yi Wang; Chia-Cheng Pai; Jun-Jie Wang; Hsiang-Ting Wen; Yu-Cheng Pai; Yao-Wen Chang; James Chien-Mo Li; Jie-Hong Roland Jiang (DAC, 2018)

Machine-learning-based dynamic IR drop prediction for ECO. - Yen-Chun Fang; Heng-Yi Lin; Min-Yan Su; Chien-Mo James Li; Eric Jia-Wei Fang (ICCAD, 2018)

Test methodology for PCHB/PCFB Asynchronous Circuits. - Ting-Yu Shen; Chia-Cheng Pai; Tsai-Chieh Chen; James Chien-Mo Li; Samuel Pan (ITC, 2018)

Parallel order ATPG for test compaction. - Yu-Wei Chen; Yu-Hao Ho; Chih-Ming Chang; Kai-Chieh Yang; Ming-Ting Li; James Chien-Mo Li (VLSI-DAT, 2018)

Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations. - Yu-Ching Li; Shih-Yao Lin 001; Heng-Yi Lin; James Chien-Mo Li (VLSI-DAT, 2018)

IR drop prediction of ECO-revised circuits using machine learning. - Shih-Yao Lin 001; Yen-Chun Fang; Yu-Ching Li; Yu-Cheng Liu; Tsung-Shan Yang; Shang-Chien Lin; Chien-Mo James Li; Eric Jia-Wei Fang (VTS, 2018)

A new method for parameter estimation of high-order polynomial-phase signals. - Runqing Cao; James Chien-Mo Li; Lei Zuo 001; Zeyu Wang 002; Yunlong Lu (Signal Process., 2018)

ATPG and Test Compression for Probabilistic Circuits. - Kai-Chieh Yang; Ming-Ting Lee; Chen-Hung Wu; James Chien-Mo Li (VLSI-DAT, 2019)

DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG. - Shih-An Hsieh; Ying-Hsu Wang; Ting-Yu Shen; Kuan-Yen Huang; Chia-Cheng Pai; Tsai-Chieh Chen; James Chien-Mo Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips. - Chih-Yan Liu; Mu-Ting Wu; James Chien-Mo Li; Gaurav Bhargava; Chris Nigh (ATS, 2020)

Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits. - Cheng-Yun Hsieh; Chen-Hung Wu; Chia-Hsien Huang; His-Sheng Goan; James Chien-Mo Li (DAC, 2020)

High Efficiency and Low Overkill Testing for Probabilistic Circuits. - Ming-Ting Lee; Chen-Hung Wu; Shi-Tang Liu; Cheng-Yun Hsieh; James Chien-Mo Li (ITC-Asia, 2020)

Automatic IR-Drop ECO Using Machine Learning. - Heng-Yi Lin; Yen-Chun Fang; Shi-Tang Liu; Jia-Xian Chen; Chien-Mo James Li; Eric Jia-Wei Fang (ITC-Asia, 2020)

Diagnosis technique for Clustered Multiple Transition Delay Faults. - Yan-Shen You; Chih-Yan Liu; Mu-Ting Wu; Po-Wei Chen; James Chien-Mo Li (ITC-Asia, 2020)

qATG: Automatic Test Generation for Quantum Circuits. - Chen-Hung Wu; Cheng-Yun Hsieh; Jiun-Yun Li; James Chien-Mo Li (ITC, 2020)

Machine Learning-Based Test Pattern Generation for Neuromorphic Chips. - Hsiao-Yin Tseng; I-Wei Chiu; Mu-Ting Wu; James Chien-Mo Li (ICCAD, 2021)

Fault Modeling and Testing of Spiking Neural Network Chips. - Yi-Zhan Hsieh; Hsiao-Yin Tseng; I-Wei Chiu; James Chien-Mo Li (ITC-Asia, 2021)

Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning. - Yen-Ting Kuo; Wei-Chen Lin; Chun Chen; Chao-Ho Hsieh; James Chien-Mo Li; Eric Jia-Wei Fang; Sung S.-Y. Hsueh (ITC, 2021)

Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization. - Mu-Ting Wu; Cheng-Sian Kuo; James Chien-Mo Li; Chris Nigh; Gaurav Bhargava (ITC, 2021)

Chip Performance Prediction Using Machine Learning Techniques. - Min-Yan Su; Wei-Chen Lin; Yen-Ting Kuo; Chien-Mo James Li; Eric Jia-Wei Fang; Sung S.-Y. Hsueh (VLSI-DAT, 2021)

Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits. - Tsai-Chieh Chen; Chia-Cheng Pai; Yi-Zhan Hsieh; Hsiao-Yin Tseng; Chien-Mo James Li; Tsung-Te Liu; I-Wei Chiu (J. Electron. Test., 2021)

Vector-based Dynamic IR-drop Prediction Using Machine Learning. - Jia-Xian Chen; Shi-Tang Liu; Yu-Tsung Wu; Mu-Ting Wu; Chien-Mo James Li; Norman Chang; Ying-Shiun Li; Wentze Chuang (ASP-DAC, 2022)

Automatic Test Configuration and Pattern Generation (ATCPG) for Neuromorphic Chips. - I-Wei Chiu; Xin-Ping Chen; Jennifer Shueh-Inn Hu; James Chien-Mo Li (ICCAD, 2022)

Low-IR-Drop Test Pattern Regeneration Using A Fast Predictor. - Shi-Tang Liu; Jia-Xian Chen; Yu-Tsung Wu; Chao-Ho Hsieh; Chien-Mo James Li; Norman Chang; Ying-Shiun Li; Wentze Chuang (ISQED, 2022)

Diagnosing Double Faulty Chains through Failing Bit Separation. - Cheng-Sian Kuo; Bing-Han Hsieh; James Chien-Mo Li; Chris Nigh; Gaurav Bhargava; Mason Chern (ITC, 2022)

ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption. - Wei-Chen Lin; Chun Chen; Chao-Ho Hsieh; James Chien-Mo Li; Eric Jia-Wei Fang; Sung S.-Y. Hsueh (ITC, 2022)

Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis. - Bing-Han Hsieh; Yun-Sheng Liu; James Chien-Mo Li; Chris Nigh; Mason Chern; Gaurav Bhargava (ITC, 2023)

High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns. - Zhe-Jia Liang; Yu-Tsung Wu; Yun-Feng Yang; James Chien-Mo Li; Norman Chang; Akhilesh Kumar; Ying-Shiun Li (ITC, 2023)

Vmin Prediction Using Nondestructive Stress Test. - Chun Chen; Jeng-Yu Liao; James Chien-Mo Li; Harry H. Chen; Eric Jia-Wei Fang (VTS, 2023)

Diagnosis of Quantum Circuits in the NISQ Era. - Yu-Min Li; Cheng-Yun Hsieh; Yen-Wei Li; James Chien-Mo Li (VTS, 2023)

Low-Complexity Algorithmic Test Generation for Neuromorphic Chips. - Hsu-Yu Huang; Chu-Yun Hsiao; Tsung-Te Liu; James Chien-Mo Li (DAC, 2024)

Test Compression for Neuromorphic Chips. - Xin-Ping Chen; Hsu-Yu Huang; Chu-Yun Hsiao; Jennifer Shueh-Inn Hu; James Chien-Mo Li (ETS, 2024)

Thermal-Aware Test Frequency Optimization. - Wei-Shen Wang; Zhe-Jia Liang; James Chien-Mo Li; Norman Chang; Akhilesh Kumar; Ying-Shiun Li (ITC-Asia, 2024)

qFD: Coherent and Depolarizing Fault Diagnosis for Quantum Processors. - Yen-Wei Li; Cheng-Yun Hsieh; Meng-Chen Wu; James Chien-Mo Li (ITC, 2024)

FeBiM: Efficient and Compact Bayesian Inference Engine Empowered with Ferroelectric In-Memory Computing. - Chao Li 065; Zhicheng Xu; Bo Wen; Ruibin Mao; Chien-Mo James Li; Thomas Kämpfe; Kai Ni 004; Xunzhao Yin (CoRR, 2024)

Small Sampling Overhead Error Mitigation for Quantum Circuits. - Cheng-Yun Hsieh; Hsin-Ying Tsai; Yuan-Hsiang Lu; James Chien-Mo Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Efficient ML-Based Transient Thermal Prediction for 3D-ICs. - Yun-Feng Yang; Wei-Shen Wang; Yung-Jen Lee; James Chien-Mo Li; Norman Chang; Akhilesh Kumar; Ying-Shiun Li; Jessica Yen; Lang Lin (ASP-DAC, 2025)

Multi-core Vmin and Worst-core Vmin Prediction using SOMAC. - Jeng-Yu Liao; Li-Yang Wang; James Chien-Mo Li; Harry H. Chen (VTS, 2025)

ML-based Adaptive Wafer Sort to Preserve Diagnostic Information. - Yun-Sheng Liu; Min-Hsin Liu; James Chien-Mo Li (VTS, 2025)