An Efficient Functional Coverage Test for HDL Descriptions at RTL. - Chien-Nan Jimmy Liu; Jing-Yang Jou (ICCD, 1999)

A novel approach for functional coverage measurement in HDL. - Chien-Nan Jimmy Liu; Chen-Yi Chang; Jing-Yang Jou; Ming-Chih Lai; Hsing-Ming Juan (ISCAS, 2000)

An Automatic Controller Extractor for HDL Descriptions at the RTL. - Chien-Nan Jimmy Liu; Jing-Yang Jou (IEEE Des. Test Comput., 2000)

An efficient design-for-verification technique for HDLs. - Chien-Nan Jimmy Liu; I-Ling Chen; Jing-Yang Jou (ASP-DAC, 2001)

Automatic Functional Vector Generation Using the Interacting FSM Model. - Chien-Nan Jimmy Liu; Chia-Chih Yen; Jing-Yang Jou (ISQED, 2001)

Effective Error Diagnosis for RTL Designs in HDLs. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (Asian Test Symposium, 2002)

An efficient IP-level power model for complex digital circuits. - Chih-Yang Hsu; Chien-Nan Jimmy Liu; Jing-Yang Jou (ASP-DAC, 2003)

A Design-for-Verification Technique for Functional Pattern Reduction. - Chien-Nan Jimmy Liu; I-Ling Chen; Jing-Yang Jou (IEEE Des. Test Comput., 2003)

An Efficient Power Model for IP-Level Complex Designs. - Chih-Yang Hsu; Chien-Nan Jimmy Liu; Jing-Yang Jou (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA. - Chin-Lung Chuang; Dong-Jung Lu; Chien-Nan Jimmy Liu (Asian Test Symposium, 2004)

On code coverage measurement for Verilog-A. - Yuan-Bin Sha; Mu-Shun Matt Lee; Chien-Nan Jimmy Liu (HLDVT, 2004)

An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (ASP-DAC, 2005)

An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs. - Chin-Cheng Kuo; Yu-Chien Wang; Chien-Nan Jimmy Liu (ACM Great Lakes Symposium on VLSI, 2005)

A novel approach for high-level power modeling of sequential circuits using recurrent neural networks. - Wen-Tsan Hsieh; Chih-Chieh Shiue; Chien-Nan Jimmy Liu (ISCAS (4), 2005)

Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (ISCAS (6), 2005)

An efficient mechanism to provide full visibility for hardware debugging. - Wei-Hsiang Cheng; Chin-Lung Chuang; Chien-Nan Jimmy Liu (ISCAS, 2006)

A Scalable Power Modeling Approach for Embedded Memory Using LIB Format. - Wen-Tsan Hsieh; Chi-Chia Yu; Chien-Nan Jimmy Liu; Yi-Fang Chiu (PATMOS, 2006)

Estimation of Loss Coefficients of Nonlinear Rubber Using Iterative H∞ Filter. - Chih-Hu Wang; Bore-Kuen Lee; Wei-Hang Tseng; Chung-Hsi Fu; Chauchin Su; Chien-Nan Jimmy Liu (SMC, 2006)

On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems. - Chin-Cheng Kuo; Chien-Nan Jimmy Liu (VLSI-SoC, 2006)

An Efficient Approach to Build Accurate Behavioral Models of PLL Designs. - Chin-Cheng Kuo; Yu-Chien Wang; Chien-Nan Jimmy Liu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems. - Wenliang Tseng; Chien-Nan Jimmy Liu; Chauchin Su (IEICE Trans. Electron., 2006)

On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design. - Chao-Hung Lu; Hung-Ming Chen; Chien-Nan Jimmy Liu (ASP-DAC, 2007)

Using power gating techniques in area-array SoC floorplan design. - Chi-Yi Yeh; Hung-Ming Chen; Li-Da Huang; Wei-Ting Wei; Chao-Hung Lu; Chien-Nan Jimmy Liu (SoCC, 2007)

Hybrid Approach to Faster Functional Verification with Full Visibility. - Chin-Lung Chuang; Wei-Hsiang Cheng; Dong-Jung Lu; Chien-Nan Jimmy Liu (IEEE Des. Test Comput., 2007)

An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model. - Wen-Tsan Hsieh; Chi-Chia Yu; Chien-Nan Jimmy Liu; Yi-Fang Chiu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Tableless Approach for High-Level Power Modeling Using Neural Networks. - Chih-Yang Hsu; Wen-Tsan Hsieh; Chien-Nan Jimmy Liu; Jing-Yang Jou (J. Inf. Sci. Eng., 2007)

Observability Analysis on HDL Descriptions for Effective Functional Validation. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Quick supply current waveform estimation at gate level using existed cell library information. - Mu-Shun Matt Lee; Chin-Hsun Lin; Chien-Nan Jimmy Liu; Shih-Che Lin (ACM Great Lakes Symposium on VLSI, 2008)

An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning. - Chao-Hung Lu; Hung-Ming Chen; Chien-Nan Jimmy Liu (J. Inf. Sci. Eng., 2008)

A Scalable Digitalized Buffer for Gigabit I/O. - Hungwen Lu; Chauchin Su; Chien-Nan Jimmy Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Long-Range Prediction for Real-Time MPEG Video Traffic: An Hinfty Filter Approach. - Chih-Hu Wang; Bor-Sen Chen; Bore-Kuen Lee; Tsu-Tian Lee; Chien-Nan Jimmy Liu; Chauchin Su (IEEE Trans. Circuits Syst. Video Technol., 2008)

Effective decap insertion in area-array SoC floorplan design. - Chao-Hung Lu; Hung-Ming Chen; Chien-Nan Jimmy Liu (ACM Trans. Design Autom. Electr. Syst., 2008)

A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level. - Chin-Cheng Kuo; Pei-Syun Lin; Chien-Nan Jimmy Liu (ASP-DAC, 2009)

Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design. - Chao-Hung Lu; Hung-Ming Chen; Chien-Nan Jimmy Liu; Wen-Yu Shih (DATE, 2009)

A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application. - Kuo-Hsing Cheng; Yu-Chang Tsai; Chien-Nan Jimmy Liu; Kai-Wei Hong; Chin-Cheng Kuo (IEICE Trans. Electron., 2009)

Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System. - Yuhwai Tseng; Chauchin Su; Chien-Nan Jimmy Liu (IEICE Trans. Commun., 2009)

Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models. - Chin-Cheng Kuo; Meng-Jung Lee; Chien-Nan Jimmy Liu; Ching-Ji Huang (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Tree-Topology Multiplexer for Multiphase Clock System. - Hungwen Lu; Chauchin Su; Chien-Nan Jimmy Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Design of an All-Digital LVDS Driver. - Hungwen Lu; Hsin-Wen Wang; Chauchin Su; Chien-Nan Jimmy Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Behavior-level yield enhancement approach for large-scaled analog circuits. - Chin-Cheng Kuo; Yen-Lung Chen; I-Ching Tsai; Li-Yu Chan; Chien-Nan Jimmy Liu (DAC, 2010)

Dynamic IR drop estimation at gate level with standard library information. - Mu-Shun Matt Lee; Kuo-Sheng Lai; Chia-Ling Hsu; Chien-Nan Jimmy Liu (ISCAS, 2010)

Automatic circuit adjustment technique for process sensitivity reduction and yield improvement. - Hsiu-Wen Li; Ren-Hong Fu; Hsin-Yu Luo; Chien-Nan Jimmy Liu (ISCAS, 2010)

Dynamic Supply Current Waveform Estimation with Standard Library Information. - Mu-Shun Matt Lee; Chien-Nan Jimmy Liu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Measuring the Transmission Characteristic of the Human Body in an Electrostatic-Coupling Intra Body Communication System Using a Square Test Stimulus. - Yuhwai Tseng; Chauchin Su; Chien-Nan Jimmy Liu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Measurement and Evaluation of the Bioelectrical Impedance of the Human Body by Deconvolution of a Square Wave. - Yuhwai Tseng; Chauchin Su; Chien-Nan Jimmy Liu (IEICE Trans. Inf. Syst., 2010)

Fast and Accurate Analysis of Supply Noise Effects in PLL With Noise Interactions. - Chin-Cheng Kuo; Chien-Nan Jimmy Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

ILP-based inter-die routing for 3D ICs. - Chia-Jen Chang; Pao-Jen Huang; Tai-Chen Chen; Chien-Nan Jimmy Liu (ASP-DAC, 2011)

Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization. - Chia-Wei Chang; Hong-Zu Chou; Kai-Hui Chang; Jie-Hong Roland Jiang; Chien-Nan Jimmy Liu; Chiu-Han Hsiao; Sy-Yen Kuo (ISQED, 2011)

Hybrid Testbench Acceleration for Reducing Communication Overhead. - Chin-Lung Chuang; Chien-Nan Jimmy Liu (IEEE Des. Test Comput., 2011)

Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits. - Chao-Hung Lu; Hung-Ming Chen; Chien-Nan Jimmy Liu (J. Inf. Sci. Eng., 2011)

Improving design verifiability by early RTL coverability analysis. - Kai-Hui Chang; Chia-Wei Chang; Jie-Hong Roland Jiang; Chien-Nan Jimmy Liu (MEMOCODE, 2012)

Reducing test point overhead with don't-cares. - Kai-Hui Chang; Chia-Wei Chang; Jie-Hong Roland Jiang; Chien-Nan Jimmy Liu (MWSCAS, 2012)

Peak wake-up current estimation at gate-level with standard library information. - Mu-Shun Matt Lee; Yi-Chu Liu; Wan-Rong Wu; Chien-Nan Jimmy Liu (VLSI-DAT, 2012)

Levelized High-Level Current Model of Logic Blocks for Dynamic Supply Noise Analysis. - Mu-Shun Matt Lee; Wei-Ting Liao; Chien-Nan Jimmy Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

A fast heuristic approach for parametric yield enhancement of analog designs. - Chien-Nan Jimmy Liu; Yen-Lung Chen; Chin-Cheng Kuo; I-Ching Tsai (ACM Trans. Design Autom. Electr. Syst., 2012)

Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects. - Yen-Lung Chen; Wan-Rong Wu; Guan-Ruei Lu; Chien-Nan Jimmy Liu (DATE, 2013)

LASER: layout-aware analog synthesis environment on laker. - Yu-Ching Liao; Yen-Lung Chen; Xian-Ting Cai; Chien-Nan Jimmy Liu; Tai-Chen Chen (ACM Great Lakes Symposium on VLSI, 2013)

A layout-aware automatic sizing approach for retargeting analog integrated circuits. - Yen-Lung Chen; Yi-Ching Ding; Yu-Ching Liao; Hsin-Ju Chang; Chien-Nan Jimmy Liu (VLSI-DAT, 2013)

Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs. - Chao-Hung Lu; Hung-Ming Chen; Chien-Nan Jimmy Liu; Wen-Yu Shih (Integr., 2013)

A novel design space reduction method for efficient simulation-based optimization. - Hsing-Han Tseng; Shiou-Wen Wang; Jian-Yu Chen; Chien-Nan Jimmy Liu (ISCAS, 2014)

Simultaneous optimization for low dropout regulator and its error amplifier with process variation. - Yen-Lung Chen; Guan-Ming Chu; Ying-Chi Lien; Ching-Mao Lee; Chien-Nan Jimmy Liu (VLSI-DAT, 2014)

Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics. - Yen-Lung Chen; Wan-Rong Wu; Chien-Nan Jimmy Liu; James Chien-Mo Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits. - Yen-Lung Chen; Wei Wu; Chien-Nan Jimmy Liu; Lei He 001 (ASP-DAC, 2015)

Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only). - Wei Wu; Peng Gu; Yen-Lung Chen; Chien-Nan Liu; Sudhakar Pamarti; Chang Wu; Lei He 001 (FPGA, 2015)

Layout-aware analog synthesis environment with yield consideration. - Hsin-Ju Chang; Yen-Lung Chen; Conan Yeh; Chien-Nan Jimmy Liu (ISQED, 2015)

Low-noise analog synthesis platform for bio-signal acquisition system. - Ying-Chi Lien; Ching-Mao Lee; Chih-Wei Li; Ban-Han Tsai; Chien-Nan Jimmy Liu (VLSI-DAT, 2015)

Wave digital filter based analog circuit emulation on FPGA. - Wei Wu; Yen-Lung Chen; Yue Ma; Chien-Nan Jimmy Liu; Jing-Yang Jou; Sudhakar Pamarti; Lei He 001 (ISCAS, 2016)

An Incremental Aging Analysis Method Based on Delta Circuit Simulation Technique. - Si-Rong He; Nguyen Cao Qui; Yu-Hsuan Kuo; Chien-Nan Jimmy Liu (ATS, 2017)

Layout placement optimization with isolation rings for high-voltage VLSI circuits. - Chih-Wei Lee; Hwa-Yi Tseng; Chi-Lien Kuo; Chien-Nan Jimmy Liu; Chin Hsia (VLSI-DAT, 2017)

A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering. - Yo-Hao Tu; Kai-Wen Yao; Minghao Huang; Yu-Yun Lin; Hao-Yu Chi; Po-Min Cheng; Pei-Yun Tsai 001; Muh-Tian Shiue; Chien-Nan Liu; Kuo-Hsing Cheng; Jia-Shiang Fu (VLSI-DAT, 2017)

Non-regression approach for the behavioral model generator in mixed-signal system verification. - Ling-Yen Song; Chun Wang; Chien-Nan Jimmy Liu; Yun-Jing Lin; Meng-Jung Lee; Yu-Lan Lo; Shu-Yi Kao (VLSI-SoC, 2017)

An Incremental Simulation Technique Based on Delta Model for Lifetime Yield Analysis. - Nguyen Cao Qui; Si-Rong He; Chien-Nan Jimmy Liu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Cluster-based delta-QMC technique for fast yield analysis. - Nguyen Cao Qui; Si-Rong He; Chien-Nan Jimmy Liu (Integr., 2017)

Performance-preserved analog routing methodology via wire load reduction. - Hao-Yu Chi; Hwa-Yi Tseng; Chien-Nan Jimmy Liu; Hung-Ming Chen (ASP-DAC, 2018)

Analog placement with current flow and symmetry constraints using PCP-SP. - Abhishek Patyal; Po-Cheng Pan; K. A. Asha; Hung-Ming Chen; Hao-Yu Chi; Chien-Nan Liu (DAC, 2018)

Spec-to-Layout Automation Flow for Buck Converters with Current-Mode Control in SOC Applications. - Hsin-Ju Hsu; Wan-Chun Chen; Long-Ching Yeh; Chien-Nan Jimmy Liu (SMACD, 2018)

Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines. - Hao-Yu Chi; Zi-Jun Lin; Chia-Hao Hung; Chien-Nan Jimmy Liu; Hung-Ming Chen (ICCAD, 2019)

A Structure-Based Methodology for Analog Layout Generation. - Yu-Hsien Chen; Hao-Yu Chi; Ling-Yen Song; Chien-Nan Jimmy Liu; Hung-Ming Chen (SMACD, 2019)

On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. - Hung-Ming Chen; Chia-Lin Hu; Kang-Yu Chang; Alexandra Küster; Yu-Hsien Lin; Po-Shen Kuo; Wei-Tung Chao; Bo-Cheng Lai; Chien-Nan Liu; Shyh-Jye Jou (ICCAD, 2020)

Achieving Analog Layout Integrity through Learning and Migration Invited Talk. - Mark Po-Hung Lin; Hao-Yu Chi; Abhishek Patyal; Zheng-Yao Liu; Jun-Jie Zhao; Chien-Nan Jimmy Liu; Hung-Ming Chen (ICCAD, 2020)

Wire Load Oriented Analog Routing with Matching Constraints. - Hao-Yu Chi; Chien-Nan Jimmy Liu; Hung-Ming Chen (ACM Trans. Design Autom. Electr. Syst., 2020)

Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design. - Hao-Yu Chi; Han-Chung Chang; Chih-Hsin Yang; Chien-Nan Liu; Jing-Yang Jou (DATE, 2021)

On Reconfiguring Memory-Centric AI Edge Devices for CIM. - Hung-Ming Chen; Cheng-En Ni; Kang-Yu Chang; Tzu-Chieh Chiang; Shih-Han Chang; Cheng-Yu Chiang; Bo-Cheng Lai; Chien-Nan Liu; Shyh-Jye Jou (ISOCC, 2021)

Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips. - Ling-Yen Song; Chih-Shen Yeh; Chien-Nan Liu; Juinn-Dar Huang (VLSI-DAT, 2021)

A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation. - Hao-Yu Chi; Zi-Jun Lin; Chia-Hao Hung; Chien-Nan Jimmy Liu; Hung-Ming Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm. - Ling-Yen Song; Tung-Chieh Kuo; Ming-Hung Wang; Chien-Nan Jimmy Liu; Juinn-Dar Huang (ASP-DAC, 2022)

Practical Substrate Design Considering Symmetrical and Shielding Routes. - Hao-Yu Chi; Simon Yi-Hung Chen; Hung-Ming Chen; Chien-Nan Liu; Yun-Chih Kuo; Ya-Hsin Chang; Kuan-Hsien Ho (DATE, 2022)

DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks. - Bo-Cheng Lai; Tzu-Chieh Chiang; Po-Shen Kuo; Wan-Ching Wang; Yan-Lin Hung; Hung-Ming Chen; Chien-Nan Liu; Shyh-Jye Jou (DATE, 2022)

Behavioral Level Simulation Framework to Support Error-Aware CNN Training with In-Memory Computing. - Shih-Han Chang; Chien-Nan Jimmy Liu; Alexandra Küster (SMACD, 2022)

On Optimizing Capacitor Array Design for Advanced Node SAR ADC. - Cheng-Yu Chiang; Chia-Lin Hu; Kang-Yu Chang; Mark Po-Hung Lin; Shyh-Jye Jou; Hung-Yu Chen; Chien-Nan Jimmy Liu; Hung-Ming Chen (SMACD, 2022)

Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy. - Kang-Yi Fan; Jyun-Hua Chen; Chien-Nan Liu; Juinn-Dar Huang (VLSI-DAT, 2022)

On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. - Cheng-Yu Chiang; Chia-Lin Hu; Mark Po-Hung Lin; Yu-Szu Chung; Shyh-Jye Jou; Jieh-Tsorng Wu; Shiuh-Hua Wood Chiang; Chien-Nan Jimmy Liu; Hung-Ming Chen (ASP-DAC, 2023)

Reshaping System Design in 3D Integration: Perspectives and Challenges. - Hung-Ming Chen; Chu-Wen Ho; Shih-Hsien Wu; Wei Lu; Po-Tsang Huang; Hao-Ju Chang; Chien-Nan Jimmy Liu (ISPD, 2023)

Layout Synthesis of Analog Primitive Cells with Variational Autoencoder. - Po-Chun Wang; Mark Po-Hung Lin; Chien-Nan Jimmy Liu; Hung-Ming Chen (SMACD, 2023)

Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization. - Ling-Yen Song; Chih-Yun Chou; Tung-Chieh Kuo; Chien-Nan Liu; Juinn-Dar Huang (ACM Trans. Design Autom. Electr. Syst., 2023)

Accurate Estimation of Buffered Interconnect Delay Based on Virtual Buffering and Multi-Level Cluster Tree Techniques. - Chen-Ho Chen; Chien-Nan Jimmy Liu; Wei-Ting Tu; Tung-Chieh Chen; Iris Hui-Ru Jiang (APCCAS, 2024)

Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization. - Bo-Han Li; Kuan-Chih Lin; Hao Zuo; Po-Cheng Pan; Hung-Ming Chen; Shyh-Jye Jou; Chien-Nan Jimmy Liu; Bo-Cheng Lai (MWSCAS, 2024)

ML/DL-Based Signal Integrity Optimization for InFO Routing. - Bo-Kai Kang; Hao-Ju Chang; Hung-Ming Chen; Chien-Nan Jimmy Liu (NewCAS, 2024)

Mitigating Power and Process Variation for Analog CIM Design Migration. - Shih-Han Chang; Shih-Yu Chen; Chun-Wen Yang; Hau-Wei Huang; Yu-Cheng Yang; Wei-Liang Chen; Chien-Nan Liu; Hung-Ming Chen (SMACD, 2024)

On Awareness of Offset-Via and Teardrop in Advanced Packaging Interconnect Synthesis. - Hao-Ju Chang; Yu-Hung Chen; Hao-Wei Huang; Yihua Yeh; Hung-Ming Chen; Chien-Nan Jimmy Liu (ASP-DAC, 2025)

Efficient Guard Ring-Aware Placement for FinFET Analog Circuits with Diffusion Sharing. - Shih-Yu Chen; Tzu-Hsiang Wei; Haoju Chang; Hung-Ming Chen; Chien-Nan Jimmy Liu (SMACD, 2025)

An LLM-assisted Analog IC Design Tool with Automatic Topology Selection and Circuit Sizing. - Anh Nguyen; Chien-Nan Jimmy Liu (SMACD, 2025)

Error-Aware Training for In-RRAM Computing Design Considering Non-Ideal Effects in RRAM Crossbar Array and Peripheral Circuits. - Shih-Han Chang; Ray-Hong Yen; Chien-Nan Liu (ACM J. Emerg. Technol. Comput. Syst., 2025)