67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process. - Chua-Chin Wang; Chien-Ping Kuo (ISCAS, 2021)

200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process. - Chua-Chin Wang; Chien-Ping Kuo (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition. - Chua-Chin Wang; Ralph Gerard B. Sangalang; Chien-Ping Kuo; Hsin-Che Wu; Yi Hsu; Shen-Fu Hsiao; Chia-Hung Yeh (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)