Gate Voltages Impacting on Latch-up Measurements. - Shao-Chang Huang; Jian-Hsing Lee; Chun-Chih Chen; Ching-Ho Li; Chih-Cherng Liao; Kai-Chieh Hsu; Gong-Kai Lin; Li-Fan Chen; Chien-Wei Wang; Chih-Hsuan Lin; Yeh-Ning Jou; Ke-Horng Chen (ICCE-TW, 2022)

EOS Endurance Power Circuits without Depletion Mode Devices. - Shao-Chang Huang; Jian-Hsing Lee; Ching-Ho Li; Sue-Yi Chen; Chih-Hsuan Lin; Chun-Chih Chen; Li-Fan Chen; Gong-Kai Lin; Chien-Wei Wang; Kai-Chieh Hsu; Szu-Chi Chen; Shang-Chuan Pai; et al. (ICCE-TW, 2022)

Bipolar Transistors' Holding Phenomena. - Shao-Chang Huang; Kai-Chieh Hsu; Chih-Hsuan Lin; Chien-Wei Wang; Ching-Ho Li; Chih-Cherng Liao; Jung-Tsun Chuang; Gong-Kai Lin; Lin-Fan Chen; Chun-Chih Chen; Yeh-Ning Jou; Jian-Hsing Lee; et al. (ICCE-Taiwan, 2023)

Optimizing Device Metal Routing Layouts by the Simulation Tool. - Shao-Chang Huang; Ching-Ho Li; Chih-Cherng Liao; Jung-Tsun Chuang; Chien-Wei Wang; Gong-Kai Lin; Lin-Fan Chen; Chun-Chih Chen; Kuan-I Ho; Che-Hua Chang; Hsiao-Ying Yang; Chung-Ren Lao; et al. (ICCE-Taiwan, 2023)

Transmission Line Pulse Width Impacting on Device Performances. - Shao-Chang Huang; Chien-Wei Wang; Chih-Hsuan Lin; Kai-Chieh Hsu; Ching-Ho Li; Chih-Cherng Liao; Jung-Tsun Chuang; Gong-Kai Lin; Lin-Fan Chen; Chun-Chih Chen; Yeh-Ning Jou; Jian-Hsing Lee; et al. (ICCE-Taiwan, 2023)

A Concise Electrothermal Model to Characterize the Thermal Safe-Operating Area of Power Transistor. - Jian-Hsing Lee; Gong-Kai Lin; Chun-Chih Chen; Li-Fan Chen; Chien-Wei Wang; Shao-Chang Huang; Ching-Ho Li; Chih-Cherng Liao; Jung-Tsun Chuang; Ke-Horng Chen (IRPS, 2023)

Strategies for Mitigating Commercial Sensor Chip Variability with Experimental Design Controls. - Eliza K. Hanson; Chien-Wei Wang; Lisa Minkoff; Rebecca J. Whelan (Sensors, 2023)

The Influence of the Block Design on the ID-VD Curves of Power Transistor for E-SOA Characterization. - Chun-Chih Chen; Shih-Chieh Chien; Chien-Wei Wang; Yu-Sheng Chiu; Jung-Tsun Chuang; Li-Fan Chen; Chieh-Yao Chuang; Jian-Hsing Lee (ICCE-Taiwan, 2024)