Low-power timing closure methodology for ultra-low voltage designs. - Wen-Pin Tu; Chung-Han Chou; Shih-Hsu Huang; Shih-Chieh Chang; Yow-Tyng Nieh; Chien-Yung Chou (ICCAD, 2013)

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. - Tay-Jyi Lin; Cheng-An Chien; Pei-Yao Chang; Ching-Wen Chen; Po-Hao Wang; Ting-Yu Shyu; Chien-Yung Chou; Shien-Chun Luo; Jiun-In Guo; Tien-Fu Chen; Gene C. H. Chuang; Yuan-Hua Chu; et al. (ISSCC, 2013)