A scalable delay insensitive asynchronous NoC with adaptive routing. - Abdulaziz Alhussien; Chifeng Wang; Nader Bagherzadeh (ICT, 2010)

Area and Power-efficient Innovative Network-on-Chip Architecurte. - Chifeng Wang; Wen-Hsiang Hu; Seung Eun Lee; Nader Bagherzadeh (PDP, 2010)

A Wireless Network-on-Chip Design for Multicore Platforms. - Chifeng Wang; Wen-Hsiang Hu; Nader Bagherzadeh (PDP, 2011)

Area and power-efficient innovative congestion-aware Network-on-Chip architecture. - Chifeng Wang; Wen-Hsiang Hu; Seung Eun Lee; Nader Bagherzadeh (J. Syst. Archit., 2011)

Design and evaluation of a high throughput robust router for network-on-chip. - Abdulaziz Alhussien; Chifeng Wang; Nader Bagherzadeh (IET Comput. Digit. Tech., 2012)

High-throughput differentiated service provision router architecture for wireless network-on-chip. - Chifeng Wang; Nader Bagherzadeh (Int. J. High Perform. Syst. Archit., 2012)

A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms. - Chifeng Wang; Wen-Hsiang Hu; Nader Bagherzadeh (Microprocess. Microsystems, 2012)

Scalable load balancing congestion-aware Network-on-Chip router architecture. - Chifeng Wang; Wen-Hsiang Hu; Nader Bagherzadeh (J. Comput. Syst. Sci., 2013)

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip. - Chifeng Wang; Nader Bagherzadeh (Microprocess. Microsystems, 2014)

Design and analysis of a mesh-based wireless network-on-chip. - Wen-Hsiang Hu; Chifeng Wang; Nader Bagherzadeh (J. Supercomput., 2015)