BIST Test Pattern Generators for Stuck-Open and Delay Testing. - Chih-Ang Chen; Sandeep K. Gupta 001 (EDAC-ETC-EUROASIC, 1994)

Low power state assignment targeting two-and multi-level logic implementations. - Chi-Ying Tsui; Massoud Pedram; Chih-Ang Chen; Alvin M. Despain (ICCAD, 1994)

A Methodology to Design Efficient BIST Test Pattern Generators. - Chih-Ang Chen; Sandeep K. Gupta (ITC, 1995)

A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts. - Chih-Ang Chen; Sandeep K. Gupta 001 (DAC, 1996)

BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms. - Chih-Ang Chen; Sandeep K. Gupta 001 (IEEE Trans. Computers, 1996)

Design of efficient BIST test pattern generators for delay testing. - Chih-Ang Chen; Sandeep K. Gupta (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Efficient BIST TPG design and test set compaction for delay testing via input reduction. - Chih-Ang Chen; Sandeep K. Gupta (ICCD, 1998)

Efficient BIST TPG design and test set compaction via input reduction. - Chih-Ang Chen; Sandeep K. Gupta (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)