Universal logic gate for FPGA design. - Chih-Chang Lin; Malgorzata Marek-Sadowska; Duane Gatlin (ICCAD, 1994)

Logic rectification and synthesis for engineering change. - Chih-Chang Lin; David Ihsin Cheng; Malgorzata Marek-Sadowska; Kuang-Chien Chen (ASP-DAC, 1995)

Logic Synthesis for Engineering Change. - Chih-Chang Lin; Kuang-Chien Chen; Shih-Chieh Chang; Malgorzata Marek-Sadowska; Kwang-Ting Cheng (DAC, 1995)

Circuit partitioning with logic perturbation. - David Ihsin Cheng; Chih-Chang Lin; Malgorzata Marek-Sadowska (ICCAD, 1995)

Cost-free scan: a low-overhead scan path design methodology. - Chih-Chang Lin; Mike Tien-Chien Lee; Malgorzata Marek-Sadowska; Kuang-Chien Chen (ICCAD, 1995)

Test Point Insertion: Scan Paths through Combinational Logic. - Chih-Chang Lin; Malgorzata Marek-Sadowska; Kwang-Ting Cheng; Mike Tien-Chien Lee (DAC, 1996)

Sequential Permissible Functions and their Application to Circuit Optimization. - Chih-Chang Lin; Malgorzata Marek-Sadowska; Kuang-Chien Chen; Mike Tien-Chien Lee (ED&TC, 1996)

On designing universal logic blocks and their application to FPGA design. - Chih-Chang Lin; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs. - Peichen Pan; Chih-Chang Lin (FPGA, 1998)

Test-point insertion: scan paths through functional logic. - Chih-Chang Lin; Malgorzata Marek-Sadowska; Kwang-Ting Cheng; Mike Tien-Chien Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Cost-free scan: a low-overhead scan path design. - Chih-Chang Lin; Malgorzata Marek-Sadowska; Mike Tien-Chien Lee; Kuang-Chien Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Logic synthesis for engineering change. - Chih-Chang Lin; Kuang-Chien Chen; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A 2.7GHz 3.9mW Mesh-BJT LC-VCO with -204dBc/Hz FOM in 65nm CMOS. - Tao-Wen Chung; Tsung-Ching Huang; S. Chung; Ming-Chieh Huang; Chih-Chang Lin; Chan-Hong Chern; Fu-Lung Hsueh (CICC, 2012)

8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS. - Tsung-Ching Huang; Tao-Wen Chung; Chan-Hong Chern; Ming-Chieh Huang; Chih-Chang Lin; Fu-Lung Hsueh (ISSCC, 2014)

A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET. - Dirk Pfaff; Robert Abbott; Xin-Jie Wang; Babak Zamanlooy; Shahaboddin Moazzeni; Raleigh Smith; Chih-Chang Lin (CICC, 2019)

A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET. - Dirk Pfaff; Shahaboddin Moazzeni; Leisheng Gao; Mei-Chen Chuang; Xin-Jie Wang; Chai Palusa; Robert Abbott; Rolando Ramirez; Maher Amer; Ming-Chieh Huang; Chih-Chang Lin; Fred Kuo; et al. (VLSI Circuits, 2019)

Design Guidelines of Social-Assisted Robots for the Elderly: A Mixed Method Systematic Literature Review. - Chih-Chang Lin; Hao-Yu Liao; Fang-Wu Tung (HCI (43), 2020)

Exploring User Engagement with Smartwatch Health Services: A Comparative Study Between Taiwan and Singapore. - Chih-Chang Lin; Fang-Wu Tung; Chien-Hsiung Chen (HCI (17), 2024)