A new cryogenic CMOS readout structure for infrared focal plane array. - Chih-Cheng Hsieh; Chung-Yu Wu; Tai-Ping Sun (IEEE J. Solid State Circuits, 1997)

Focal-plane-arrays and CMOS readout techniques of infrared imaging systems. - Chih-Cheng Hsieh; Chung-Yu Wu; Far-Wen Jih; Tai-Ping Sun (IEEE Trans. Circuits Syst. Video Technol., 1997)

High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA. - Chih-Cheng Hsieh; Chung-Yu Wu; Tai-Ping Sun; Far-Wen Jih; Ya-Tung Cherng (IEEE J. Solid State Circuits, 1998)

A High Performance Linear Current Mode Image Sensor. - Chih-Cheng Hsieh; Wei-Yu Chen; Chung-Yu Wu (ISCAS, 2009)

A new rail-to-rail comparator with adaptive power control for low power SAR ADCs in biomedical application. - Sung-Min Chin; Chih-Cheng Hsieh; Chin-Fong Chiu; Hann-Huei Tsai (ISCAS, 2010)

A 0.8V 64×64 CMOS imager with integrated sense-and-stimulus pixel for artificial retina applications. - Chin-Lin Lee; Chih-Cheng Hsieh (A-SSCC, 2011)

A new CMOS image sensor readout structure for 3D integrated imagers. - Shang-Fu Yeh; Jin-Yi Lin; Chih-Cheng Hsieh; Ka-Yi Yeh; Chung-Chi Jim Li (CICC, 2011)

Live demonstration: The prototype of real-time image pre-processing system for satellites' remote sensing. - Tsan-Jieh Chen; Chih-Hui Weng; Herming Chiueh; Chih-Cheng Hsieh; Shang-Fu Yeh; Wen-Hsu Chang; Ying-Zong Juang; Hann-Huei Tsai; Chin-Fong Chiu (ISCAS, 2011)

A 0.6V CMOS Image Sensor with in-pixel biphasic current driver for biomedical application. - Chin-Lin Lee; Chih-Cheng Hsieh (ISCAS, 2011)

A Low-Power Electronic Nose Signal-Processing Chip for a Portable Artificial Olfaction System. - Kea-Tiong Tang; Shih-Wen Chiu; Meng-Fan Chang; Chih-Cheng Hsieh; Jyuo-Min Shyu (IEEE Trans. Biomed. Circuits Syst., 2011)

A 9.2b 47fJ/conversion-step asynchronous SAR ADC with input range prediction DAC switching. - Hsin-Yuan Huang; Jin-Yi Lin; Chih-Cheng Hsieh; Wen-Hsu Chang; Hann-Huei Tsai; Chin-Fong Chiu (ISCAS, 2012)

A 0.5V 4.95μW 11.8fps PWM CMOS imager with 82dB dynamic range and 0.055% fixed-pattern noise. - Meng-Ting Chung; Chih-Cheng Hsieh (ISSCC, 2012)

Time-delay integration readout with adjacent pixel signal transfer for CMOS image sensor. - Kuo-Wei Cheng; Chin Yin; Chih-Cheng Hsieh; Wen-Hsu Chang; Hann-Huei Tsai; Chin-Fong Chiu (VLSI-DAT, 2012)

Exploration of Second-Order Effects in High-Performance Continuous-Time ΣΔ Modulators Using Discrete-Time Models. - Wei-Lin Chen; Chih-Cheng Hsieh (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS. - Chang-Yuan Liou; Chih-Cheng Hsieh (ISSCC, 2013)

A 1V 14kfps smart CMOS imager with tracking and edge-detection modes for biomedical monitoring. - Chin Yin; Chih-Cheng Hsieh (VLSI-DAT, 2013)

A 0.5 V PWM CMOS Imager With 82 dB Dynamic Range and 0.055% Fixed-Pattern-Noise. - Meng-Ting Chung; Chin-Lin Lee; Chin Yin; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2013)

A 3 Megapixel 100 Fps 2.8 µm Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers. - Shang-Fu Yeh; Chih-Cheng Hsieh; Ka-Yi Yeh (IEEE J. Solid State Circuits, 2013)

2.4-GHz 10-Mb/s BFSK Embedded Transmitter With a Stacked-LC DCO for Wireless Testing Systems. - Chi-Ying Lee; Chih-Cheng Hsieh; Jenn-Chyou Bor (IEEE Trans. Very Large Scale Integr. Syst., 2013)

24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia. - Kea-Tiong Tang; Shih-Wen Chiu; Chung-Hung Shih; Chia-Ling Chang; Chia-Min Yang; Da-Jeng Yao; Jen-Huo Wang; Chien-Ming Huang 005; Hsin Chen; Kwuang-Han Chang; Chih-Cheng Hsieh; Ting-Hau Chang; et al. (ISSCC, 2014)

A signal acquisition and processing chip with built-in cluster for chemiresistive gas sensor array. - Shih-Wen Chiu; Jen-Huo Wang; Kwuang-Han Chang; Hsiang-Chiu Wu; Hsin Chen; Chih-Cheng Hsieh; Meng-Fan Chang; Guoxing Wang; Kea-Tiong Tang (NEWCAS, 2014)

A dual-mode CMOS image sensor for optical wireless communication. - Chih-Hao Lin; Chih-Cheng Hsieh; Che-Chun Lin; Ren-Jr Chen (VLSI-DAT, 2014)

A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90nm CMOS. - Yan-Jiun Chen; Chih-Cheng Hsieh (VLSIC, 2014)

A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia. - Shih-Wen Chiu; Jen-Huo Wang; Kwuang-Han Chang; Ting-Hau Chang; Chia-Min Wang; Chia-Lin Chang; Chen-Ting Tang; Chien-Fu Chen; Chung-Hung Shih; Han-Wen Kuo; Li-Chun Wang 001; Hsin Chen; et al. (IEEE Trans. Biomed. Circuits Syst., 2014)

A 132dB DR readout IC with pulse width modulation for IR focal plane arrays. - Chia-Chi Kuo; Chih-Cheng Hsieh (A-SSCC, 2015)

A 1.2V 1MS/s 7.65fJ/conversion-step 12-bit hybrid SAR ADC with time-to-digital converter. - Sung-En Hsieh; Cheng-Kang Ho; Chih-Cheng Hsieh (ISCAS, 2015)

An 8-bit column-shared SAR ADC for CMOS image sensor applications. - Jin-Yi Lin; Kwuang-Han Chang; Chen-Che Kao; Shih-Chin Lo; Yan-Jiun Chen; Pei-Chen Lee; Chi-Hui Chen; Chin Yin; Chih-Cheng Hsieh (ISCAS, 2015)

An in-pixel equalizer with kTC noise cancellation and FPN reduction for time-of-flight CMOS image sensor. - Zheng-Wei Huang; Chin-Fong Chiu; Chih-Cheng Hsieh (VLSI-DAT, 2015)

A 0.4V self-powered CMOS imager with 140dB dynamic range and energy harvesting. - Albert Yen-Chih Chiou; Chih-Cheng Hsieh (VLSIC, 2015)

A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS. - Jin-Yi Lin; Chih-Cheng Hsieh (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS. - Kwuang-Han Chang; Chih-Cheng Hsieh (A-SSCC, 2016)

An integrated CMOS optical sensing chip for multiple bio-signal detections. - Albert Yen-Chih Chiou; Sung-En Hsieh; Yan-Quan Pan; Chia-Chi Kuo; Chih-Cheng Hsieh (A-SSCC, 2016)

A time delay multiple integration linear CMOS image sensor for multispectral satellite telemetry. - Kuan-Lin Liu; Chih-Cheng Hsieh; Sheng-Yeh Lai; Chin-Fong Chiu (A-SSCC, 2016)

Design of a 0.5 V 1.68mW nose-on-a-chip for rapid screen of chronic obstructive pulmonary disease. - Ting-I Chou; Shih-Wen Chiu; Kwuang-Han Chang; Yi-Ju Chen; Chen-Ting Tang; Chung-Hung Shih; Chih-Cheng Hsieh; Meng-Fan Chang; Chia-Hsiang Yang; Herming Chiueh; Kea-Tiong Tang (BioCAS, 2016)

A hybrid CMOS-imager with perovskites as photoactive layer. - Pei-Wen Yen; Yan-Rung Lin; Sheng-Min Yu; Shiu-Cheng Lou; Kai-Ping Chuang; Bor-Nian Chuang; Albert Yen-Chih Chiou; Chih-Cheng Hsieh (IEEE SENSORS, 2016)

A 0.3V 0.705fJ/conversion-step 10-bit SAR ADC with shifted monotonie switching scheme in 90nm CMOS. - Sung-En Hsieh; Chih-Cheng Hsieh (ISCAS, 2016)

A 0.4V 1.94fJ/conversion-step 10b 750kS/s SAR ADC with input-range-adaptive switching. - Pei-Chen Lee; Chen-Che Kao; Chih-Cheng Hsieh (ISCAS, 2016)

A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC. - Sung-En Hsieh; Chih-Cheng Hsieh (VLSI Circuits, 2016)

A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS. - Yan-Jiun Chen; Kwuang-Han Chang; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2016)

A 137 dB Dynamic Range and 0.32 V Self-Powered CMOS Imager With Energy Harvesting Pixels. - Albert Yen-Chih Chiou; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2016)

A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS. - Sung-En Hsieh; Chih-Cheng Hsieh (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching. - Pei-Chen Lee; Jin-Yi Lin; Chih-Cheng Hsieh (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization. - Chen-Che Kao; Sung-En Hsieh; Chih-Cheng Hsieh (A-SSCC, 2017)

A CMOS time of flight (TOF) depth image sensor with in-pixel background cancellation and sensitivity improvement using phase shifting readout technique. - Ting Liao; Nien-An Lee; Chih-Cheng Hsieh (A-SSCC, 2017)

A CMOS imaging platform using single photon avalanche diode array in standard technology. - Tzu-Hsiang Hsu; Chih-Cheng Hsieh (IEEE SENSORS, 2017)

A Hybrid Analog-to-Digital Conversion Algorithm With Sub-Radix and Multiple Quantization Thresholds. - Kwuang-Han Chang; Chih-Cheng Hsieh (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS. - Jin-Yi Lin; Chih-Cheng Hsieh (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with Continuous-Time Feedforward Cascaded (CTFC) Op-Amps. - Kwuang-Han Chang; Chih-Cheng Hsieh (A-SSCC, 2018)

A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference Rejections. - Hsiang-Lin Chen; Sung-En Hsieh; Tzu-Hsiang Hsu; Chih-Cheng Hsieh (A-SSCC, 2018)

A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array. - Pin-Yi Li; Cheng-Han Yang; Wei-Hao Chen; Jian-Hao Huang; Wei-Chen Wei; Je-Syu Liu; Wei-Yu Lin; Tzu-Hsiang Hsu; Chih-Cheng Hsieh; Ren-Shuo Liu; Meng-Fan Chang; Kea-Tiong Tang (BioCAS, 2018)

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors. - Wei-Hao Chen; Kai-Xiang Li; Wei-Yu Lin; Kuo-Hsiang Hsu; Pin-Yi Li; Cheng-Han Yang; Cheng-Xin Xue; En-Yu Yang; Yen-Kai Chen; Yun-Sheng Chang; Tzu-Hsiang Hsu; Ya-Chin King; et al. (ISSCC, 2018)

A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator. - Sung-En Hsieh; Chih-Cheng Hsieh (ISSCC, 2018)

A 12-bit 150-MS/s Sub-Radix-3 SAR ADC With Switching Miller Capacitance Reduction. - Kwuang-Han Chang; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2018)

A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC. - Sung-En Hsieh; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2018)

A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization. - Sung-En Hsieh; Chen-Che Kao; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2018)

A CMOS Time-of-Flight Depth Image Sensor With In-Pixel Background Light Cancellation and Phase Shifting Readout Technique. - Tzu-Hsiang Hsu; Ting Liao; Nien-An Lee; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2018)

A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip. - Ting-I Chou; Kwuang-Han Chang; Jia-Yin Jhang; Shih-Wen Chiu; Guoxing Wang; Chia-Hsiang Yang; Herming Chiueh; Hsin Chen; Chih-Cheng Hsieh; Meng-Fan Chang; Kea-Tiong Tang (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction. - Tzu-Hsiang Hsu; Yen-Kai Chen; Tai-Hsing Wen; Wei-Chen Wei; Yi-Ren Chen; Fu-Chun Chang; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh (A-SSCC, 2019)

A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors. - Zhixiao Zhang; Jia-Jing Chen; Xin Si; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Yen-Cheng Chiu; Je-Min Hong; Shyh-Shyuan Sheu; Sih-Han Li; et al. (A-SSCC, 2019)

A 40MS/s 12-bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting. - Yung-Te Chang; Min-Rui Wu; Chih-Cheng Hsieh (ISCAS, 2019)

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. - Xin Si; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; Yen-Cheng Chiu; Wei-Chen Wei; Ssu-Yen Wu; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; et al. (ISSCC, 2019)

A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors. - Cheng-Xin Xue; Wei-Hao Chen; Je-Syu Liu; Jia-Fang Li; Wei-Yu Lin; Wei-En Lin; Jing-Hong Wang; Wei-Chen Wei; Ting-Wei Chang; Tung-Cheng Chang; Tsung-Yuan Huang; Hui-Yao Kao; et al. (ISSCC, 2019)

A Current-Mode Differential Sensing CMOS Imager for Optical Linear Encoder. - You-Shin Chen; Tzu-Hsiang Hsu; Chien-Wen Chen; Chih-Cheng Hsieh (VLSI-DAT, 2019)

Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices. - Kea-Tiong Tang; Wei-Chen Wei; Zuo-Wei Yeh; Tzu-Hsiang Hsu; Yen-Cheng Chiu; Cheng-Xin Xue; Yu-Chun Kuo; Tai-Hsing Wen; Mon-Shu Ho; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; et al. (VLSI Circuits, 2019)

A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors. - Kwuang-Han Chang; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2019)

A Calibration-Free 13-Bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded Op-Amps. - Kwuang-Han Chang; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2019)

An ULV PWM CMOS Imager With Adaptive-Multiple-Sampling Linear Response, HDR Imaging, and Energy Harvesting. - Albert Yen-Chih Chiou; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2019)

A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator. - Sung-En Hsieh; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2019)

A Monolithic Optical Encoder using CMOS Image Sensor with Background Light Cancellation. - You-Shin Chen; Tzu-Hsiang Hsu; Guan-Cheng Chen; Chien-Wen Chen; Chih-Cheng Hsieh (ISCAS, 2020)

5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel. - Tzu-Hsiang Hsu; Yen-Kai Chen; Jun-Shen Wu; Wen-Chien Ting; Cheng-Te Wang; Chen-Fu Yeh; Syuan-Hao Sie; Yi-Ren Chen; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; et al. (ISSCC, 2020)

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Zhixiao Zhang; Syuan-Hao Sie; et al. (ISSCC, 2020)

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Zhixiao Zhang; Hongwu Jiang; et al. (ISSCC, 2020)

15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices. - Cheng-Xin Xue; Tsung-Yuan Huang; Je-Syu Liu; Ting-Wei Chang; Hui-Yao Kao; Jing-Hong Wang; Ta-Wei Liu; Shih-Ying Wei; Sheng-Po Huang; Wei-Chen Wei; Yi-Ren Chen; Tzu-Hsiang Hsu; et al. (ISSCC, 2020)

MARS: Multi-macro Architecture SRAM CIM-Based Accelerator with Co-designed Compressed Neural Networks. - Syuan-Hao Sie; Jye-Luen Lee; Yi-Ren Chen; Chih-Cheng Lu; Chih-Cheng Hsieh; Meng-Fan Chang; Kea-Tiong Tang (CoRR, 2020)

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. - Yen-Cheng Chiu; Zhixiao Zhang; Jia-Jing Chen; Xin Si; Ruhui Liu; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Je-Min Hung; Shyh-Shyuan Sheu; et al. (IEEE J. Solid State Circuits, 2020)

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. - Xin Si; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Qiang Li 021; Meng-Fan Chang; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; et al. (IEEE J. Solid State Circuits, 2020)

Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors. - Cheng-Xin Xue; Ting-Wei Chang; Tung-Cheng Chang; Hui-Yao Kao; Yen-Cheng Chiu; Chun-Ying Lee; Ya-Chin King; Chrong Jung Lin; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Wei-Hao Chen; et al. (IEEE J. Solid State Circuits, 2020)

A Bio-Inspired Motion Detection Circuit Model for the Computation of Optical Flow: The Spatial-Temporal Filtering Reichardt Model. - Hsin-Yu Wu; Wei-Tse Kao; Harrison Hao-Yu Ku; Cheng-Te Wang; Chih-Cheng Hsieh; Ren-Shuo Liu; Kea-Tiong Tang; Chung-Chuan Lo (AICAS, 2021)

Integer Quadratic Integrate-and-Fire (IQIF): A Neuron Model for Digital Neuromorphic Systems. - Wen-Chieh Wu; Chen-Fu Yeh; Alexander James White; Cheng-Te Wang; Zuo-Wei Yeh; Chih-Cheng Hsieh; Ren-Shuo Liu; Kea-Tiong Tang; Chung-Chuan Lo (AICAS, 2021)

A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter. - Chih-Cheng Chen; Chih-Cheng Hsieh (A-SSCC, 2021)

A 12-Bit SAR ADC with Reference Voltage Ripple Suppression. - Wei-Chih Lai; Tzu-Hsiang Hsu; Chih-Cheng Chen; Chih-Cheng Hsieh (ISCAS, 2021)

Session 27 Overview: Discrete-Time ADCs Data Converters Subcommittee. - John Keane; Chih-Cheng Hsieh; Bob Verbruggen (ISSCC, 2021)

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Tianlong Pan; Sih-Han Li; Shih-Chieh Chang; et al. (ISSCC, 2021)

A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices. - Cheng-Xin Xue; Je-Min Hung; Hui-Yao Kao; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Peng Chen; Ta-Wei Liu; Chuan-Jia Jhang; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; et al. (ISSCC, 2021)

A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel. - Tzu-Hsiang Hsu; Yen-Kai Chen; Min-Yang Chiu; Guan-Cheng Chen; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2021)

A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction. - Tzu-Hsiang Hsu; Yi-Ren Chen; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2021)

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Yen-Lin Chung; William Shih; et al. (IEEE J. Solid State Circuits, 2021)

A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations. - Yen-Cheng Chiu; Chia-Sheng Yang; Shih-Hsih Teng; Hsiao-Yu Huang; Fu-Chun Chang; Yuan Wu 009; Yu-An Chien; Fang-Ling Hsieh; Chung-Yuan Li; Guan-Yi Lin; Po-Jung Chen; Tsen-Hsiang Pan; et al. (ISSCC, 2022)

A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification. - Tzu-Hsiang Hsu; Guan-Cheng Chen; Yi-Ren Chen; Chung-Chuan Lo; Ren-Shuo Liu; Meng-Fan Chang; Kea-Tiong Tang; Chih-Cheng Hsieh (ISSCC, 2022)

An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices. - Je-Min Hung; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Tai-Hao Wen; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; et al. (ISSCC, 2022)

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (ISSCC, 2022)

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Yen-Lin Chung; Jin-Sheng Ren; et al. (IEEE J. Solid State Circuits, 2022)

MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks. - Syuan-Hao Sie; Jye-Luen Lee; Yi-Ren Chen; Zuo-Wei Yeh; Zhaofang Li; Chih-Cheng Lu; Chih-Cheng Hsieh; Meng-Fan Chang; Kea-Tiong Tang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices. - Yen-Cheng Chiu; Win-San Khwa; Chung-Yuan Li; Fang-Ling Hsieh; Yu-An Chien; Guan-Yi Lin; Po-Jung Chen; Tsen-Hsiang Pan; De-Qi You; Fang-Yi Chen; Andrew Lee; Chung-Chuan Lo; et al. (ISSCC, 2023)

A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W. - Wei-Hsing Huang; Tai-Hao Wen; Je-Min Hung; Win-San Khwa; Yun-Chen Lo; Chuan-Jia Jhang; Hung-Hsi Hsu; Yu-Hsiang Chin; Yu-Chiao Chen; Chuna-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; et al. (ISSCC, 2023)

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (ISSCC, 2023)

A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices. - Tai-Hao Wen; Je-Min Hung; Hung-Hsi Hsu; Yuan Wu 009; Fu-Chun Chang; Chung-Yuan Li; Chih-Han Chien; Chin-I Su; Win-San Khwa; Jui-Jen Wu; Chung-Chuan Lo; Ren-Shuo Liu; et al. (VLSI Technology and Circuits, 2023)

A -20°C +107°C 52mk-NETD Reference-cell-free 15-bits ROIC for 80×60 Micro-bolometer Thermal Imager. - Hsin Yu; John Carl Joel Salao Marquez; Chih-Cheng Hsieh (VLSI Technology and Circuits, 2023)

8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices. - Je-Min Hung; Tai-Hao Wen; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; et al. (IEEE J. Solid State Circuits, 2023)

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Tianlong Pan; Chuan-Jia Jhang; Wei-Hsing Huang; et al. (IEEE J. Solid State Circuits, 2023)

A 12-ENOB Second-Order Noise-Shaping SAR ADC With PVT-Insensitive Voltage- Time-Voltage Converter. - Chih-Cheng Chen; Yu-Hsiang Huang; John Carl Joel Salao Marquez; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2023)

A Multimode Vision Sensor With Temporal Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing Using Stereo Vision. - Min-Yang Chiu; Guan-Cheng Chen; Tzu-Hsiang Hsu; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2023)

A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification. - Tzu-Hsiang Hsu; Guan-Cheng Chen; Yi-Ren Chen; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2023)

A nMOS-Only Pulse-Width Modulation CMOS Imager with Body Effect Mitigation Using Differential Comparison Technique. - Yu-Tang Shen; John Carl Joel Salao Marquez; Chih-Cheng Hsieh (A-SSCC, 2024)

34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices. - Win-San Khwa; Ping-Chun Wu; Jui-Jen Wu; Jian-Wei Su; Ho-Yu Chen; Zhao-En Ke; Ting-Chien Chiu; Jun-Ming Hsu; Chiao-Yen Cheng; Yu-Chen Chen; Chung-Chuan Lo; Ren-Shuo Liu; et al. (ISSCC, 2024)

34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices. - Tai-Hao Wen; Hung-Hsi Hsu; Win-San Khwa; Wei-Hsing Huang; Zhao-En Ke; Yu-Hsiang Chin; Hua-Jin Wen; Yu-Chen Chang; Wei-Ting Hsu; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; et al. (ISSCC, 2024)

A Low-OSR 5th-Order Noise Shaping SAR ADC Using EF-EF-CIFF Structure with PVT-Robust Differential V-T-V Converter. - Pao-Shu Liu; Yu-Hsiang Huang; Chih-Cheng Hsieh (VLSI Technology and Circuits, 2024)

A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro. - De-Qi You; Win-San Khwa; Jui-Jen Wu; Chuan-Jia Jhang; Guan-Yi Lin; Po-Jung Chen; Ting-Chien Chiu; Fang-Yi Chen; Andrew Lee; Yu-Cheng Hung; Chung-Chuan Lo; Ren-Shuo Liu; et al. (VLSI Technology and Circuits, 2024)

An algorithm for solving over-determined multivariate quadratic systems over finite fields. - Lih-Chung Wang; Tzer-jen Wei; Jian-Ming Shih; Yuh-Hua Hu; Chih-Cheng Hsieh (Adv. Math. Commun., 2024)

A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme. - Hung-Hsi Hsu; Tai-Hao Wen; Wei-Hsing Huang; Win-San Khwa; Yun-Chen Lo; Chuan-Jia Jhang; Yu-Hsiang Chin; Yu-Chiao Chen; Chung-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; Chih-Cheng Hsieh; et al. (IEEE J. Solid State Circuits, 2024)

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (IEEE J. Solid State Circuits, 2024)

An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices. - De-Qi You; Yen-Cheng Chiu; Win-San Khwa; Chung-Yuan Li; Fang-Ling Hsieh; Yu-An Chien; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; Tsung-Yung Jonathan Chang; et al. (IEEE J. Solid State Circuits, 2024)

8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. - Jian-Wei Su; Pei-Jung Lu; Ping-Chun Wu; Yen-Chi Chou; Ta-Wei Liu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Wei-Hsing Huang; Chih-Han Chien; Peng-I Mei; Sih-Han Li; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (IEEE J. Solid State Circuits, 2024)

14.2 A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices. - Win-San Khwa; Ping-Chun Wu; Jian-Wei Su; Chiao-Yen Cheng; Jun-Ming Hsu; Yu-Chen Chen; Le-Jung Hsieh; Jyun-Cheng Bai; Yu-Sheng Kao; Tsung-Han Lou; Ashwin Sanjay Lele; Jui-Jen Wu; et al. (ISSCC, 2025)

14.1 A 22nm 104.5TOPS/W µ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks. - De-Qi You; Win-San Khwa; Bo Zhang; Fang-Yi Chen; Andrew Lee; Yu-Cheng Hung; Yi-Ming Li; Yu-Hui Wang; Chung-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; Chih-Cheng Hsieh; et al. (ISSCC, 2025)

A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device. - Hung-Hsi Hsu; Tai-Hao Wen; Win-San Khwa; Wei-Hsing Huang; Zhao-En Ke; Yu-Hsiang Chin; Hua-Jin Wen; Yu-Chen Chang; Wei-Ting Hsu; Ashwin Sanjay Lele; Bo Zhang; Ping-Sheng Wu; et al. (IEEE J. Solid State Circuits, 2025)

An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips. - Ping-Chun Wu; Win-San Khwa; Jui-Jen Wu; Jian-Wei Su; Chuan-Jia Jhang; Ho-Yu Chen; Zhao-En Ke; Ting-Chien Chiu; Jun-Ming Hsu; Chiao-Yen Cheng; Yu-Chen Chen; Chung-Chuan Lo; et al. (IEEE J. Solid State Circuits, 2025)