Iteration-Level Parallel Execution of DO Loops with a Reduced Set of Dependence Relations. - Zen Chen; Chih-Chi Chang (J. Parallel Distributed Comput., 1987)

On the Design of VLSI Architectures for Parallel Execution of DO Loops. - Zen Chen; Chih-Chi Chang; Tsorng-Lin Chia (J. Parallel Distributed Comput., 1990)

A New Algorithm and its VLSI Architecture Design for Connected Component Labelling. - Shuenn-Der Jean; Chi-Min Liu; Chih-Chi Chang; Zen Chen (ISCAS, 1994)

A neural-fuzzy controller with heterogeneous neurons. - Chih-Chi Chang; Chungyong Tsai (IJCNN, 1999)

A neural network controller based on the rule of bang-bang control. - Chungyong Tsai; Chih-Chi Chang (IJCNN, 1999)

High-frequency and power-efficiency ultrasound beam-forming processor for handheld applications. - Guo-Zua Wu; Song-Nien Tang; Chih-Chi Chang; Chien-Ju Lee; Kuan-Hsien Lin; Oscal T.-C. Chen (SoCC, 2014)

Minimizing Response Time for MapReduce Applications on In-Storage Processing Architecture. - Zheng-Yang Lu; Chih-Chi Chang; Ya-Shu Chen (ISPACS, 2021)