Efficient Test Methodologies for Conditional Sum Adders. - Jin-Fu Li 001; Chih-Chiang Hsu (Asian Test Symposium, 2004)

A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs. - Tsu-Wei Tseng; Jin-Fu Li 001; Chih-Chiang Hsu; Alex Pao; Kevin Chiu; Eliot Chen (ITC, 2006)

A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances. - Chung-Fu Lin; Chia-Fu Huang; De-Chung Lu; Chih-Chiang Hsu; Wen-Tsung Chiu; Yu-Wei Chen; Yeong-Jar Chang (ITC, 2008)

Online Scheduling of Workflow Applications in Grid Environment. - Chih-Chiang Hsu; Kuo-Chan Huang; Feng-Jian Wang (GPC, 2010)

ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs. - Tsu-Wei Tseng; Jin-Fu Li 001; Chih-Chiang Hsu (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. - Hao-I Yang; Shih-Chi Yang; Mao-Chih Hsia; Yung-Wei Lin; Yi-Wei Lin; Chien-Hen Chen; Chi-Shin Chang; Geng-Cing Lin; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; et al. (SoCC, 2011)

Online scheduling of workflow applications in grid environments. - Chih-Chiang Hsu; Kuo-Chan Huang; Feng-Jian Wang (Future Gener. Comput. Syst., 2011)

High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. - Hao-I Yang; Yi-Wei Lin; Mao-Chih Hsia; Geng-Cing Lin; Chi-Shin Chang; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Nan-Chun Lien; Hung-Yu Li; Kuen-Di Lee; et al. (ISCAS, 2012)

A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. - Yung-Wei Lin; Hao-I Yang; Mao-Chih Hsia; Yi-Wei Lin; Chien-Hen Chen; Ching-Te Chuang; Wei Hwang; Nan-Chun Lien; Kuen-Di Lee; Wei-Chiang Shih; Ya-Ping Wu; Wen-Ta Lee; et al. (SoCC, 2012)