Bounding the Execution Times of DMA I/O Tasks on Hard-Real-Time Embedded Systems. - Tai-Yi Huang; Chih-Chieh Chou; Po-Yuan Chen (RTCSA, 2003)

Communication-driven task binding for multiprocessor with latency insensitive network-on-chip. - Liang-Yu Lin; Cheng-Yeh Wang; Pao-Jui Huang; Chih-Chieh Chou; Jing-Yang Jou (ASP-DAC, 2005)

Bounding DMA Interference on Hard-Real-Time Embedded Systems. - Tai-Yi Huang; Chih-Chieh Chou; Po-Yuan Chen (J. Inf. Sci. Eng., 2006)

A Necessary and Sufficient Condition for the Construction of 2-to-1 Optical FIFO Multiplexers by a Single Crossbar Switch and Fiber Delay Lines. - Chih-Chieh Chou; Cheng-Shang Chang; Duan-Shin Lee; Jay Cheng (IEEE Trans. Inf. Theory, 2006)

vNVML: An Efficient User Space Library for Virtualizing and Sharing Non-Volatile Memories. - Chih-Chieh Chou; Jaemin Jung; A. L. Narasimha Reddy; Paul V. Gratz; Doug Voigt (MSST, 2019)

Optimizing Post-Copy Live Migration with System-Level Checkpoint Using Fabric-Attached Memory. - Chih-Chieh Chou; Yuan Chen 001; Dejan S. Milojicic; A. L. Narasimha Reddy; Paul Gratz (MCHPC@SC, 2019)

Virtualize and share non-volatile memories in user space. - Chih-Chieh Chou; Jaemin Jung; A. L. Narasimha Reddy; Paul V. Gratz; Doug Voigt (CCF Trans. High Perform. Comput., 2020)

Reducing Minor Page Fault Overheads through Enhanced Page Walker. - Chandrahas Tirumalasetty; Chih-Chieh Chou; A. L. Narasimha Reddy; Paul Gratz; Ayman Abouelwafa (ACM Trans. Archit. Code Optim., 2022)