A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths. - Jiun-In Guo; Chien-Chang Lin; Chih-Da Chien (J. Circuits Syst. Comput., 2002)

A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining. - Jiun-In Guo; Chih-Da Chien; Chien-Chang Lin (ISCAS (5), 2003)

A high-performance MPEG4 bitstream processing core. - Tai-Lun Chang; Ying-Ming Tsai; Chih-Da Chien; Chien-Chang Lin; Jiun-In Guo (ICME, 2004)

A power-aware IP core generator for the one-dimensional discrete Fourier transform. - Chih-Da Chien; Chien-Chang Lin; Jiun-In Guo; Tien-Fu Chen (ISCAS (3), 2004)

A low-power motion compensation IP core design for MPEG-1/2/4 video decoding. - Chih-Da Chien; Ho-Chun Chen; Lin-Chieh Huang; Jiun-In Guo (ISCAS (5), 2005)

A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications. - Chih-Da Chien; Keng-Po Lu; Yi-Hung Shih; Jiun-In Guo (ISCAS, 2006)

An Area-Efficient Variable Length Decoder IP Core Design for MPEG-1/2/4 Video Coding Applications. - Chih-Da Chien; Keng-Po Lu; Yu-Min Chen; Jiun-In Guo; Yuan-Sun Chu; Ching-Lung Su (IEEE Trans. Circuits Syst. Video Technol., 2006)

A Low Latency Memory Controller for Video Coding Systems. - Chih-Da Chien; Chih-Wei Wang; Chiun-Chau Lin; Tien-Wei Hsieh; Yuan-Hwa Chu; Jiun-In Guo (ICME, 2007)

A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation. - Guo-An Jian; Chih-Da Chien; Jiun-In Guo (ISCAS, 2007)

A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications. - Chih-Da Chien; Chien-Chang Lin; Yi-Hung Shih; He-Chun Chen; Chia-Jui Huang; Cheng-Yen Yu; Chih-Liang Chen; Ching-Hwa Cheng; Jiun-In Guo (ISSCC, 2007)

A Multi-standard Video Decoder for High Definition Video Applications. - Cheng-An Chien; Chih-Da Chien; Jui-Chin Chu; Jiun-In Guo; Ching-Hwa Cheng (ISCAS, 2009)

A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. - Chih-Da Chien; Cheng-An Chien; Jui-Chin Chu; Jiun-In Guo; Ching-Hwa Cheng (ACM Trans. Design Autom. Electr. Syst., 2009)

18.6 A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications. - Chi-Cheng Ju; Tsu-Ming Liu; Kun-Bin Lee; Yung-Chang Chang; Han-Liang Chou; Chih-Ming Wang; Tung-Hsing Wu; Hue-Min Lin; Yi-Hsin Huang; Chia-Yun Cheng; Ting-An Lin; Chun-Chia Chen; et al. (ISSCC, 2015)

A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications. - Chi-Cheng Ju; Tsu-Ming Liu; Kun-Bin Lee; Yung-Chang Chang; Han-Liang Chou; Chih-Ming Wang; Tung-Hsing Wu; Hue-Min Lin; Yi-Hsin Huang; Chia-Yun Cheng; Ting-An Lin; Chun-Chia Chen; et al. (IEEE J. Solid State Circuits, 2016)