On processor allocation in hypercube multiprocessors. - Chih-Hao Huang; Ting-Lu Huang; Jie-Yong Juang (COMPSAC, 1989)

A Partial Compaction Scheme for Processor Allocation in Hypercube Multiprocessors. - Chih-Hao Huang; Jie-Yong Juang (ICPP (1), 1990)

Information caching in the execution of logic programs. - Chih-Hao Huang; Jie-Yong Juang (COMPSAC, 1991)

A flexible design of a decision feedback equalizer and a novel CCK technique for wireless LAN systems. - Hsin-Lei Lin; Robert Chen-Hao Chang; Chih-Hao Huang; Hongchin Lin (ISCAS (2), 2003)

The Fermilab Data Storage Infrastructure. - Jon Bakken; Eileen Berman; Chih-Hao Huang; Alexander Moibenko; Donald Petravick; Michael Zalokar (IEEE Symposium on Mass Storage Systems, 2003)

Fermilab's Multi-Petabyte Scalable Mass Storage System. - Gene Oleynik; Bonnie Alcorn; Wayne Baisley; Jon Bakken; David Berg; Eileen Berman; Chih-Hao Huang; Terry Jones; Robert D. Kennedy; Alexander Kulyavtsev; Alexander Moibenko; Timur Perelmutov; et al. (MSST, 2005)

An RFID Application Model for the Publication Industry: A Taiwan Perspective. - James T. Lin; Jiang-Liang Hou; Wei-Ching Chen; Chih-Hao Huang (Int. J. Electron. Bus. Manag., 2005)

Asymptotic Distribution of The Number of Isolated Nodes in Wireless Ad Hoc Networks with Unreliable Nodes and Links. - Chih-Wei Yi; Peng-Jun Wan; Kuo-Wei Lin; Chih-Hao Huang (GLOBECOM, 2006)

Quantitative performance evaluation of RFID applications in the supply chain of the printing industry. - Jiang-Liang Hou; Chih-Hao Huang (Ind. Manag. Data Syst., 2006)

A Model for Document Validation Using Concurrent Authentication Processes. - Jiang-Liang Hou; Chih-Hao Huang (J. Comput. Inf. Syst., 2008)

Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique. - Jin-Fu Lin; Soon-Jyh Chang; Chih-Hao Huang (Asian Test Symposium, 2009)

Algorithms for the determination of document authentication time and the recommendation of document modification. - Jiang-Liang Hou; Chih-Hao Huang (Expert Syst. Appl., 2009)

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation. - Chun-Cheng Liu; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin; Chung-Ming Huang; Chih-Hao Huang; Linkai Bu; Chih-Chung Tsai (ISSCC, 2010)

Distributed Analysis in CMS. - Alessandra Fanfani; M. Anzar Afaq; Jose Afonso Sanches; Julia Andreeva; Giuseppe Bagliesi; Lothar Bauerdick; Stefano Belforte; Patricia Bittencourt Sampaio; Kenneth Bloom; Barry Blumenfeld; Daniele Bonacorsi; Chris Brew; et al. (J. Grid Comput., 2010)

A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique. - Jin-Fu Lin; Soon-Jyh Chang; Chun-Cheng Liu; Chih-Hao Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction. - Jin-Fu Lin; Soon-Jyh Chang; Te-Chieh Kung; Hsin-Wen Ting; Chih-Hao Huang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Hardware Resource Reliability Analysis based on Deep Learning for Virtual Machine Deployment Optimization. - Chih-Hao Huang; Bo-Hong Huang; Tin-Yu Wu (GCCE, 2020)

Measuring Outcomes in Healthcare Economics using Artificial Intelligence: with Application to Resource Allocation. - Feras A. Batarseh; Chih-Hao Huang (FLAIRS, 2021)

Measuring Outcomes in Healthcare Economics using Artificial Intelligence: with Application to Resource Management. - Chih-Hao Huang; Feras A. Batarseh; Adel Boueiz; Ajay Kulkarni; Po-Hsuan Su; Jahan Aman (CoRR, 2021)

A survey on artificial intelligence assurance. - Feras A. Batarseh; Laura J. Freeman; Chih-Hao Huang (J. Big Data, 2021)