An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In DAC-Segmentation/ELD-Compensation 6b 960MS/s SAR-Quantizer in 28nm LP for 802.11ax Applications. - Chi-Yun Wang; Jen-Huan Tsai; Sheng-Yuan Su; Jen-Che Tsai; Jhy-Rong Chen; Chih-Hong Lou (ISSCC, 2019)