A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS. - Ying-Zu Lin; Chih-Hou Tsai; Shan-Chih Tsou; Chao-Hsin Lu (VLSI Circuits, 2016)

A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET. - Ying-Zu Lin; Chin-Yu Lin; Shan-Chih Tsou; Chih-Hou Tsai; Chao-Hsin Lu (ISSCC, 2019)

An 80MHz-BW 640MS/s Time-Interleaved Passive Noise- Shaping SAR ADC in 22nm FDSOI Process. - Chin-Yu Lin; Ying-Zu Lin; Chih-Hou Tsai; Chao-Hsin Lu (ISSCC, 2021)