A World-Band Triple-Mode 802.11a/b/g SOC in 130-nm CMOS. - Jie-Wei Lai; Chia-Hsin Wu; Anson Lin; Wei-Kai Hong; Cheng-Yu Wang; Chih-Hsien Shen; Yu-Hsin Lin; Yi-Hsien Cho; YangChuan Chen; Yuan-Hung Chung (IEEE J. Solid State Circuits, 2009)

A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS. - Yuan-Hung Chung; Min Chen; Wei-Kai Hong; Jie-Wei Lai; Sheng-Jau Wong; Chien-Wei Kuan; Hong-Lin Chu; Chihun Lee; Chih-Fan Liao; Hsuan-Yu Liu; Hong-Kai Hsu; Li-Chun Ko; et al. (ISSCC, 2012)

28.2 A 0.29mm2 frequency synthesizer in 40nm CMOS with 0.19psrms jitter and. - YuLi Hsueh; Lan-Chou Cho; Chih-Hsien Shen; Yi-Chien Tsai; Tzu-Chan Chueh; Tao-Yao Chang; Jui-Lin Hsu; Jing-Hong Conan Zhan (ISSCC, 2014)

7.3 A 40nm low-power transceiver for LTE-A Carrier Aggregation. - Chinq-Shiun Chiu; Shih-Chieh Yen; Chi-Yao Yu; Tzung-Han Wu; Chung-Yun Chou; Sheng-Che Tseng; Chih-Hsien Shen; Yu-Tsung Lu; Hsinhung Chen; Song-Yu Yang; Yen-Tso Chen; Guang-Kaai Dehng; et al. (ISSCC, 2017)

19.3 A Fractional-N PLL with 34fsrms Jitter and -255.5dB FoM Based on a Multipath Feedback Technique. - Chao-Ching Hung; Chih-Hsien Shen; Chien-Li Lin; Mou Tzou; Kevin Fong; Yu-Li Hsueh (ISSCC, 2025)