VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems. - Jen-Chih Kuo; Ching-Hua Wen; Chih-Hsiu Lin; An-Yeu Wu (EURASIP J. Adv. Signal Process., 2003)

A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes. - Cheng-Shing Wu; An-Yeu Wu; Chih-Hsiu Lin (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

Low cost decision feedback equalizer (DFE) design for Giga-bit systems. - Chih-Hsiu Lin; An-Yeu Wu (ICASSP (3), 2005)

Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications. - Chih-Hsiu Lin; An-Yeu Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture. - Chih-Hsiu Lin; An-Yeu Wu (IEEE Trans. Signal Process., 2005)

High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems. - Chih-Hsiu Lin; An-Yeu Wu; Fan-Min Li (IEEE Trans. Circuits Syst. II Express Briefs, 2006)