A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links. - Chih-Kong Ken Yang; Mark A. Horowitz (IEEE J. Solid State Circuits, 1996)

A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling. - Chih-Kong Ken Yang; Ramin Farjad-Rad; Mark A. Horowitz (IEEE J. Solid State Circuits, 1998)

High-speed electrical signaling: overview and limitations. - Mark Horowitz; Chih-Kong Ken Yang; Stefanos Sidiropoulos (IEEE Micro, 1998)

A 14-bit, 10-Msamples/s D/A converter using multibit ΣΔ modulation. - Katayoun Falakshahi; Chih-Kong Ken Yang; Bruce A. Wooley (IEEE J. Solid State Circuits, 1999)

A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter. - Ramin Farjad-Rad; Chih-Kong Ken Yang; Mark A. Horowitz; Thomas H. Lee (IEEE J. Solid State Circuits, 1999)

A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver. - Ramin Farjad-Rad; Chih-Kong Ken Yang; Mark A. Horowitz; Thomas H. Lee (IEEE J. Solid State Circuits, 2000)

A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS. - Chih-Kong Ken Yang; Vladimir Stojanovic; Siamak Modjtahedi; Mark A. Horowitz; William F. Ellersick (IEEE J. Solid State Circuits, 2001)

Jitter optimization based on phase-locked loop design parameters. - Mozhgan Mansuri; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2002)

Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops. - Mozhgan Mansuri; Dean Liu; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2002)

CMOS LC oscillator using variable mean frequency. - Ping-Hsuan Hsieh; Jack Judy; Chih-Kong Ken Yang (CICC, 2003)

Analysis of timing recovery for multi-Gbps PAM transceivers. - Chih-Kong Ken Yang; Koon-Lun Jackie Wong (CICC, 2003)

A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation. - Mozhgan Mansuri; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2003)

Methodology for on-chip adaptive jitter minimization in phase-locked loops. - Mozhgan Mansuri; A. Hadiashar; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A 27-mW 3.6-gb/s I/O transceiver. - Jackie Koon Lun Wong; Hamid Hatamkhani; Mozhgan Mansuri; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2004)

Offset compensation in comparators with minimum input-referred supply noise. - Koon-Lun Jackie Wong; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2004)

Power-centric design of high-speed I/Os. - Hamid Hatamkhani; Frank Lambrecht; Vladimir Stojanovic; Chih-Kong Ken Yang (DAC, 2006)

An 8Gb/s Transformer-Boosted Transmitter with >V00 swing. - Jintae Kim; Hamid Hatamkhani; Chih-Kong Ken Yang (ISSCC, 2006)

A Serial-Link Transceiver with Transition Equalization. - Koon-Lun Jackie Wong; Chih-Kong Ken Yang (ISSCC, 2006)

A sub-10-ps multiphase sampling system using redundancy. - Li-min Lee; Daniel Weinlader; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2006)

Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference. - Jan Van der Spiegel; Ram K. Krishnamurthy; Sreedhar Natarajan; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2006)

A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration. - Aida Varzaghani; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2006)

A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter. - Aida Varzaghani; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2006)

A Study of the Optimal Data Rate for Minimum Power of I/Os. - Hamid Hatamkhani; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A Comprehensive Phase-Transfer Model for Delay-Locked Loops. - James R. Burnham; Gu-Yeon Wei; Chih-Kong Ken Yang; Haitham A. Hindi (CICC, 2007)

Device-circuit co-optimization for mixed-mode circuit design via geometric programming. - Jintae Kim; Ritesh Jhaveri; Jason Woo; Chih-Kong Ken Yang (ICCAD, 2007)

An Adaptive Low-Jitter LC-Based Clock Distribution. - Li-min Lee; Chih-Kong Ken Yang (ISSCC, 2007)

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE. - Azita Emami-Neyestanak; Aida Varzaghani; John F. Bulzacchelli; Alexander V. Rylyakov; Chih-Kong Ken Yang; Daniel J. Friedman (IEEE J. Solid State Circuits, 2007)

A Large-Swing Transformer-Boosted Serial Link Transmitter With > VDD Swing. - Jintae Kim; Hamid Hatamkhani; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2007)

A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions. - Jackie Koon Lun Wong; Alexander V. Rylyakov; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2007)

Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs. - Ping-Hsuan Hsieh; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies. - Jaeseo Lee; Geoff Hatcher; Lieven Vandenberghe; Chih-Kong Ken Yang (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage. - Ping-Hsuan Hsieh; Jay Maxey; Chih-Kong Ken Yang (CICC, 2008)

Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric. - E-Hung Chen; Jihong Ren; Brian S. Leibowitz; Hae-Chang Lee; Qi Lin; Kyung Suk Oh; Frank Lambrecht; Vladimir Stojanovic; Jared Zerbe; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2008)

Edge and Data Adaptive Equalization of Serial-Link Transceivers. - Jackie Koon Lun Wong; E-Hung Chen; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2008)

A Comprehensive Delay Model for CMOS CML Circuits. - Utku Seckin; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A nonlinear phase detector for digital phase locked loops. - Ping-Hsuan Hsieh; Jay Maxey; Chih-Kong Ken Yang (CICC, 2009)

A stochastic jitter model for analyzing digital timing-recovery circuits. - James R. Burnham; Chih-Kong Ken Yang; Haitham A. Hindi (DAC, 2009)

Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages. - Ping-Hsuan Hsieh; Jay Maxey; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2009)

An LC-Based Clock Buffer With Tunable Injection Locking. - Li-min Lee; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2009)

A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization. - Aida Varzaghani; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2009)

Clocking Links in Multi-chip Packages: A Case Study. - Tamer A. Ali 001; Dinesh Patil; Frankie Liu; Elad Alon; Jon K. Lexau; Chih-Kong Ken Yang; Ron Ho (Hot Interconnects, 2010)

A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology. - Ping-Hsuan Hsieh; Jay Maxey; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2010)

Convex Piecewise-Linear Modeling Method for Circuit Optimization via Geometric Programming. - Jintae Kim; Lieven Vandenberghe; Chih-Kong Ken Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

ADC-Based Serial I/O Receivers. - E-Hung Chen; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Guest Editorial for Special Issue on High-Performance Multichip Interconnections. - Vladimir Stojanovic; Chih-Kong Ken Yang; Ron Ho (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 4.6GHz MDLL with -46dBc reference spur and aperture position tuning. - Tamer A. Ali 001; Amr Amin Hafez; Robert J. Drost; Ronald Ho; Chih-Kong Ken Yang (ISSCC, 2011)

Scalability and design-space analysis of a 1T-1MTJ memory cell. - Richard Dorrance; Fengbo Ren; Yuta Toriyama; Amr Amin Hafez; Chih-Kong Ken Yang; Dejan Markovic (NANOARCH, 2011)

Analysis of STT-RAM cell design with multiple MTJs per access. - Henry Park; Richard Dorrance; Amr Amin Hafez; Fengbo Ren; Dejan Markovic; Chih-Kong Ken Yang (NANOARCH, 2011)

Design and Optimization of Multipath Ring Oscillators. - Amr Amin Hafez; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links. - Jaeha Kim; E-Hung Chen; Jihong Ren; Brian S. Leibowitz; Patrick Satarzadeh; Jared Zerbe; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Multilevel Power Optimization of Pipelined A/D Converters. - Jintae Kim; S. Limotyrakis; Chih-Kong Ken Yang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A low-power highly multiplexed parallel PRBS generator. - Ming-Shuan Chen; Chih-Kong Ken Yang (CICC, 2012)

A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs). - Fengbo Ren; Henry Park; Richard Dorrance; Yuta Toriyama; Chih-Kong Ken Yang; Dejan Markovic (ISQED, 2012)

A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding. - Tamer A. Ali 001; Won Ho Park; Preeti Mulage; E-Hung Chen; Ron Ho; Chih-Kong Ken Yang (VLSIC, 2012)

Power Optimized ADC-Based Serial Link Receiver. - E-Hung Chen; Ramy Yousry; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2012)

Nearly Exact Analytical Formulation of the DNL Yield of the Digital-to-Analog Converter. - Henry Park; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A bipolar >40-V driver in 45-nm SOI CMOS technology. - Yousr Ismail; Chang-Jin Kim 001; Chih-Kong Ken Yang (CICC, 2013)

A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS. - Ramy Yousry; Henry Park; E-Hung Chen; Chih-Kong Ken Yang (ISCAS, 2013)

A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS. - Amr Amin Hafez; Ming-Shuan Chen; Chih-Kong Ken Yang (ISSCC, 2013)

A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding. - Tamer A. Ali 001; Robert J. Drost; Ron Ho; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2013)

A 0.1-1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection. - Ming-Shuan Chen; Amr Amin Hafez; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2013)

In Situ SRAM Static Stability Estimation in 65-nm CMOS. - Henry Park; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2013)

Analysis and Design of Superharmonic Injection-Locked Multipath Ring Oscillators. - Amr Amin Hafez; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

An INL Yield Model of the Digital-to-Analog Converter. - Henry Park; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs. - Fengbo Ren; Henry Park; Chih-Kong Ken Yang; Dejan Markovic (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Effects of Using Advanced Cooling Systems on the Overall Power Consumption of Processors. - Won Ho Park; Chih-Kong Ken Yang (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A 12-V charge pump-based square wave driver in 65-nm CMOS technology. - Yousr Ismail; Chih-Kong Ken Yang (A-SSCC, 2014)

A 50-64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS. - Ming-Shuan Chen; Chih-Kong Ken Yang (CICC, 2014)

A compact stacked-device output driver in low-voltage CMOS Technology. - Yousr Ismail; Chih-Kong Ken Yang (ISCAS, 2014)

23.8 A 34V charge pump in 65nm bulk CMOS technology. - Yousr Ismail; Haechang Lee; Sudhakar Pamarti; Chih-Kong Ken Yang (ISSCC, 2014)

Flexible-Assignment Calibration Technique for Mismatch-Constrained Digital-to-Analog Converters. - Jintae Kim; Siamak Modjtahedi; Chih-Kong Ken Yang (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression. - Henry Park; Chih-Kong Ken Yang (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Effects of Active Cooling on Workload Management in High Performance Processors. - Won Ho Park; Chih-Kong Ken Yang (CLOSER, 2015)

A low-PDP and low-area repeater using passive CTLE for on-chip interconnects. - Ming-Shuan Chen; Mau-Chung Frank Chang; Chih-Kong Ken Yang (VLSIC, 2015)

A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology. - Ming-Shuan Chen; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2015)

A 32-48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology. - Amr Amin Hafez; Ming-Shuan Chen; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2015)

A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters. - Jintae Kim; Siamak Modjtahedi; Chih-Kong Ken Yang (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology. - Yousr Ismail; Haechang Lee; Sudhakar Pamarti; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2017)

A 19-GHz Pulsed-Coherent ToF Receiver With 40-μm Precision for Laser Ranging Systems. - Li-Yang Chen; Chih-Kong Ken Yang (ESSCIRC, 2019)

An 8.5pJ/bit Ultra-Low Power Wake-Up Receiver Using Schottky Diodes for IoT Applications. - Mahmoud R. Elhebeary; Li-Yang Chen; Sudhakar Pamarti; Chih-Kong Ken Yang (ESSCIRC, 2019)

An 85%-Efficiency Hybrid DC-DC Converter for Sub-Microwatt IoT Applications. - Mahmoud R. Elhebeary; Chih-Kong Ken Yang (MWSCAS, 2019)

A 92%-Efficiency Battery Powered Hybrid DC-DC Converter for IoT Applications. - Mahmoud R. Elhebeary; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst., 2020)

A Class-D FVF LDO With Multi-Level PWM Gate Control, 280-ns Settling Time, and No Overshoot/Undershoot. - Mahmoud R. Elhebeary; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst., 2020)

A 6μm-Precision Pulsed-Coherent Lidar with a 40-dB Tuning Range Inverter-Based Phase-Invariant PGA. - Li-Yang Chen; Abhinav Kumar Vinod; James F. McMillan; Chee Wei Wong; Chih-Kong Ken Yang (CICC, 2021)

A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS. - Yan Zhang 050; Chia-Jen Liang; Christopher Chen; Andrew Liu; Jason Woo; Sudhakar Pamarti; Chih-Kong Ken Yang; Mau-Chung Frank Chang (ESSCIRC, 2021)

A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS. - Liangxiao Tang; Weixin Gai; Chih-Kong Ken Yang; Bingyi Ye; Congcong Chen (ISCAS, 2021)

A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input. - Jiazhang Song; Li-Yang Chen; Mau-Chung Frank Chang; Sudhakar Pamarti; Chih-Kong Ken Yang (ISCAS, 2022)

A Pulsed-Coherent Lidar With Sub-10 μm Precision. - Li-Yang Chen; Abhinav Kumar Vinod; James F. McMillan; Hangbo Yang; Chee Wei Wong; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2022)

A Scalable 20V Charge-Pump-Based Driver in 65nm CMOS Technology. - Mostafa Toubar; Yousr Ismail; Sameh Ibrahim; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Sub-Sampling 35GHz PLL in 45nm PDSOI BiCMOS with 37fs Integrated Jitter and a FoM of -252dB. - Christopher Chen; Yan Zhang 050; Hao-Yu Chien; Jiazhang Song; Jia Zhou; Chao-Jen Tien; Sudhakar Pamarti; Chih-Kong Ken Yang; Mau-Chung Frank Chang (BCICTS, 2024)

Cryogenic Alternative: CMOS Versus Dynamic-Based Logic. - Ali H. Hassan; Puneet Gupta 001; Sudhakar Pamarti; Chih-Kong Ken Yang (MWSCAS, 2024)

Invited Paper: A Pseudo-Differential Architecture for Low-Power Voltage-to-Time Converters. - Ali H. Hassan; Hassan Mostafa; Chih-Kong Ken Yang (MWSCAS, 2024)

A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation. - Zhichao Chen; Ali H. Hassan; Rhesa Ramadhan; Yingheng Li; Chih-Kong Ken Yang; Sudhakar Pamarti; Puneet Gupta 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)