Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles. - Iris Hui-Ru Jiang; Hua-Yu Chang; Chih-Long Chang (ISPD, 2010)

INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs. - Iris Hui-Ru Jiang; Chih-Long Chang; Yu-Ming Yang; Evan Y.-W. Tsai; Lancer S.-F. Chen (ISPD, 2011)

Novel pulsed-latch replacement based on time borrowing and spiral clustering. - Chih-Long Chang; Iris Hui-Ru Jiang; Yu-Ming Yang; Evan Y.-W. Tsai; Aki S.-H. Chen (ISPD, 2012)

INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving. - Iris Hui-Ru Jiang; Chih-Long Chang; Yu-Ming Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

WiT: Optimal Wiring Topology for Electromigration Avoidance. - Iris Hui-Ru Jiang; Hua-Yu Chang; Chih-Long Chang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating. - Chih-Long Chang; Iris Hui-Ru Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)