An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. - Chih-Hao Liu; Shau-Wei Yen; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee; Yar-Sun Hsu; Shyh-Jye Jou (IEEE J. Solid State Circuits, 2008)

A 11.5-Gbps LDPC decoder based on CP-PEG code construction. - Chih-Lung Chen; Kao-Shou Lin; Hsie-Chia Chang; Wai-Chi Fang; Chen-Yi Lee (ESSCIRC, 2009)

Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. - Chih-Hao Liu; Chien-Ching Lin; Shao-Wei Yen; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee; Yar-Sun Hsu; Shyh-Jye Jou (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System. - Yi-Min Lin; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE J. Solid State Circuits, 2010)

Non-repetitive encoding with increased degree-1 encoding symbols for LT codes. - Kuo-Kuang Yen; Yen-Chin Liao; Chih-Lung Chen; Hsie-Chia Chang (APCCAS, 2012)

Stochastic decoding for LDPC convolutional codes. - Xin-Ru Lee; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2012)

An improved LT encoding scheme with extended chain lengths. - Kuo-Kuang Yen; Chih-Lung Chen; Hsie-Chia Chang (ISITA, 2012)

A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder. - Chih-Lung Chen; Yu-Hsiang Lin; Hsie-Chia Chang; Chen-Yi Lee (IEEE J. Solid State Circuits, 2012)

A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications. - Shao-Wei Yen; Shiang-Yu Hung; Chih-Lung Chen; Hsie-Chia Chang; Shyh-Jye Jou; Chen-Yi Lee (IEEE J. Solid State Circuits, 2012)

Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes. - Kuo-Kuang Yen; Yen-Chin Liao; Chih-Lung Chen; Hsie-Chia Chang (WCSP, 2013)

An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes. - Hsiu-Chi Chang; Chih-Lung Chen; Hsie-Chia Chang (IEEE Commun. Lett., 2013)

Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes. - Kuo-Kuang Yen; Yen-Chin Liao; Chih-Lung Chen; Hsie-Chia Chang (IEEE Commun. Lett., 2013)

Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection. - Kuo-Kuang Yen; Yen-Chin Liao; Chih-Lung Chen; John K. Zao; Hsie-Chia Chang (IEEE Trans. Multim., 2013)

A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. - Chih-Lung Chen; Sheng-Jhan Wu; Hsie-Chia Chang; Chen-Yi Lee (A-SSCC, 2014)

Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. - Chih-Wen Yang; Xin-Ru Lee; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2014)

A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications. - Chang-Hung Tsai; Tung-Yu Wu; Shu-Yu Hsu; Chia-Ching Chu; Fang-Ju Ku; Ying-Siou Laio; Chih-Lung Chen; Wing Hung Wong; Hsie-Chia Chang; Chen-Yi Lee (VLSIC, 2014)

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. - Xin-Ru Lee; Chih-Wen Yang; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2015)

A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. - Kin-Chu Ho; Chih-Lung Chen; Yen-Chin Liao; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2015)

A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications. - Xin-Ru Lee; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes. - Xin-Ru Lee; Chih-Wen Yang; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture. - Chia-Lung Lin; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. - Chia-Lung Lin; Rong-Jie Liu; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (A-SSCC, 2016)

An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm. - Chia-Lung Lin; Shu-Wen Tu; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory. - Kin-Chu Ho; Chih-Lung Chen; Hsie-Chia Chang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Towards Accurate and Efficient Classification of Power System Contingencies and Cyber-Attacks Using Recurrent Neural Networks. - Wei-Chih Hong; Ding-Ray Huang; Chih-Lung Chen; Jung-San Lee (IEEE Access, 2020)

Preserving indomitable DDoS vitality through resurrection social hybrid botnet. - Chit-Jie Chew; Ying-Chin Chen; Jung-San Lee; Chih-Lung Chen; Kuo-Yu Tsai (Comput. Secur., 2021)

A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration. - Yong-Ru Lu; Shen-Iuan Liu; Yu-Che Yang; Han-Chang Kang; Chih-Lung Chen; Ka-Un Chan; Ying-Hsi Lin (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

CoNN-IDS: Intrusion detection system based on collaborative neural networks and agile training. - Jung-San Lee; Ying-Chin Chen; Chit-Jie Chew; Chih-Lung Chen; Thu-Nguyet Huynh; Chung-Wei Kuo (Comput. Secur., 2022)