BIST design optimization for large-scale embedded memory cores. - Tzuo-Fan Chien; Wen-Chi Chao; James Chien-Mo Li; Yao-Wen Chang; Kuan-Yu Liao; Ming-Tung Chang; Min-Hsiu Tsai; Chih-Mou Tseng (ICCAD, 2009)

TSV redundancy: Architecture and design issues in 3D IC. - Ang-Chih Hsieh; TingTing Hwang; Ming-Tung Chang; Min-Hsiu Tsai; Chih-Mou Tseng; Hung-Chun Li (DATE, 2010)

Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs. - Szu-Pang Mu; Yi-Ming Wang; Hao-Yu Yang; Mango Chia-Tso Chao; Shi-Hao Chen; Chih-Mou Tseng; Tsung-Ying Tsai (ICCAD, 2010)

Test clock domain optimization for peak power supply noise reduction during scan. - Jen-Yang Wen; Yu-Chuan Huang; Min-Hong Tsai; Kuan-Yu Liao; James Chien-Mo Li; Ming-Tung Chang; Min-Hsiu Tsai; Chih-Mou Tseng; Hung-Chun Li (ITC, 2011)