Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs. - Chih-Sheng Hou; Jin-Fu Li 001; Che-Wei Chou (DELTA, 2010)

Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost. - Tsu-Wei Tseng; Chih-Sheng Hou; Jin-Fu Li 001 (VTS, 2010)

A Built-in Method to Repair SoC RAMs in Parallel. - Tsu-Wei Tseng; Jin-Fu Li 001; Chih-Sheng Hou (IEEE Des. Test Comput., 2010)

Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults. - Jin-Fu Li 001; Tsu-Wei Tseng; Chih-Sheng Hou (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Memory Built-in Self-Repair Planning Framework for RAMs in SoCs. - Chih-Sheng Hou; Jin-Fu Li 001; Tsu-Wei Tseng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Disturbance fault testing on various NAND flash memories. - Chih-Sheng Hou; Jin-Fu Li 001 (ETS, 2012)

An FPGA-based test platform for analyzing data retention time distribution of DRAMs. - Chih-Sheng Hou; Jin-Fu Li 001; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (VLSI-DAT, 2013)

Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs. - Chih-Sheng Hou; Jin-Fu Li 001 (VTS, 2013)

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. - Yun-Chao You; Chih-Sheng Hou; Li-Jung Chang; Jin-Fu Li 001; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (VTS, 2013)

Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. - Kuan-Te Wu; Jin-Fu Li 001; Yun-Chao Yu; Chih-Sheng Hou; Chi-Chun Yang; Ding-Ming Kwai; Yung-Fa Chou; Chih-Yen Lo (ATS, 2014)

Testing Disturbance Faults in Various NAND Flash Memories. - Chih-Sheng Hou; Jin-Fu Li 001 (J. Electron. Test., 2014)

A BIST Scheme With the Ability of Diagnostic Data Compression for RAMs. - Chih-Sheng Hou; Jin-Fu Li 001; Ting-Jun Fu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy. - Chih-Sheng Hou; Jin-Fu Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. - Chih-Sheng Hou; Yong-Xiao Chen; Jin-Fu Li 001; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (ITC, 2016)