A built-in self-test and self-diagnosis scheme for embedded SRAM. - Chih-Wea Wang; Chi-Feng Wu; Jin-Fu Li 001; Cheng-Wen Wu; Tony Teng; Kevin Chiu; Hsiao-Ping Lin (Asian Test Symposium, 2000)

Error Catch and Analysis for Semiconductor Memories Using March Tests. - Chi-Feng Wu; Chih-Tsun Huang; Chih-Wea Wang; Kuo-Liang Cheng; Cheng-Wen Wu (ICCAD, 2000)

A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. - Chih-Wea Wang; Ruey-Shing Tzeng; Chi-Feng Wu; Chih-Tsun Huang; Cheng-Wen Wu; Shi-Yu Huang; Shyh-Horng Lin; Hsin-Po Wang 002 (Asian Test Symposium, 2001)

Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. - Chi-Feng Wu; Chih-Tsun Huang; Kuo-Liang Cheng; Chih-Wea Wang; Cheng-Wen Wu (DAC, 2001)

Test Scheduling and Test Access Architecture Optimization for System-on-Chip. - Huan-Shan Hsu; Jing-Reng Huang; Kuo-Liang Cheng; Chih-Wea Wang; Chih-Tsun Huang; Cheng-Wen Wu; Youn-Long Lin (Asian Test Symposium, 2002)

Test Scheduling of BISTed Memory Cores for SOC. - Chih-Wea Wang; Jing-Reng Huang; Yen-Fu Lin; Kuo-Liang Cheng; Chih-Tsun Huang; Cheng-Wen Wu; Youn-Long Lin (Asian Test Symposium, 2002)

RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. - Kuo-Liang Cheng; Jen-Chieh Yeh; Chih-Wea Wang; Chih-Tsun Huang; Cheng-Wen Wu (VTS, 2002)

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. - Chih-Wea Wang; Chi-Feng Wu; Jin-Fu Li 001; Cheng-Wen Wu; Tony Teng; Kevin Chiu; Hsiao-Ping Lin (J. Electron. Test., 2002)

FAME: A Fault-Pattern Based Memory Failure Analysis Framework. - Kuo-Liang Cheng; Chih-Wea Wang; Jih-Nung Lee; Yung-Fa Chou; Chih-Tsun Huang; Cheng-Wen Wu (ICCAD, 2003)

Fault Pattern Oriented Defect Diagnosis for Memories. - Chih-Wea Wang; Kuo-Liang Cheng; Jih-Nung Lee; Yung-Fa Chou; Chih-Tsun Huang; Cheng-Wen Wu; Frank Huang; Hong-Tzer Yang (ITC, 2003)

Test and Diagnosis of Word-Oriented Multiport Memories. - Chih-Wea Wang; Kuo-Liang Cheng; Chih-Tsun Huang; Cheng-Wen Wu (VTS, 2003)

Failure Factor Based Yield Enhancement for SRAM Designs. - Yu-Tsao Hsing; Chih-Wea Wang; Ching-Wei Wu; Chih-Tsun Huang; Cheng-Wen Wu (DFT, 2004)

An SOC Test Integration Platform and Its Industrial Realization. - Kuo-Liang Cheng; Jing-Reng Huang; Chih-Wea Wang; Chih-Yen Lo; Li-Ming Denq; Chih-Tsun Huang; Shin-Wei Hung; Jye-Yuan Lee (ITC, 2004)

STEAC: A Platform for Automatic SOC Test Integration. - Chih-Yen Lo; Chen-Hsing Wang; Kuo-Liang Cheng; Jing-Reng Huang; Chih-Wea Wang; Shin-Moe Wang; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Test for more than pass/fail using on-chip temperature sensor. - Chih-Wea Wang; Chen-Tung Lin; Chun-Chieh Hsu; Ching-Tung Wu; Chi-Feng Wu (VLSI-DAT, 2012)

Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model. - Yu-Ju Shih; Chih-Tsun Huang; Jing-Jia Liou; Jyu-Yuan Lai; Chih-Wea Wang; Chi-Feng Wu (VLSI-DAT, 2017)