Real-Time Configuration for Fault-Tolerant VLSI Array Processors. - Sun-Yuan Kung; Chih-Wei Jim Chang; Chein-Wei Jen (RTSS, 1986)

Graceful Degradation Schemes for Static/Dynamic Wavefront Arrays. - Shiann-Ning Jean; Chih-Wei Jim Chang; Sun-Yuan Kung (ICPP (1), 1988)

Fault-Tolerant Array Processors Using Single-Track Switches. - Sun-Yuan Kung; Shiann-Ning Jean; Chih-Wei Jim Chang (IEEE Trans. Computers, 1989)

Fast post-placement rewiring using easily detectable functional symmetries. - Chih-Wei Jim Chang; Chung-Kuan Cheng; Peter Suaris; Malgorzata Marek-Sadowska (DAC, 2000)

Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques. - Chih-Wei Jim Chang; Kai Wang 011; Malgorzata Marek-Sadowska (DAC, 2001)

In-place delay constrained power optimization using functional symmetries. - Chih-Wei Jim Chang; Bo Hu 006; Malgorzata Marek-Sadowska (DATE, 2001)

Who are the alternative wires in your neighborhood? (alternative wires identification without search). - Chih-Wei Jim Chang; Malgorzata Marek-Sadowska (ACM Great Lakes Symposium on VLSI, 2001)

Single-Pass Redundancy Addition and Removal. - Chih-Wei Jim Chang; Malgorzata Marek-Sadowska (ICCAD, 2001)

ATPG-based logic synthesis: an overview. - Chih-Wei Jim Chang; Malgorzata Marek-Sadowska (ICCAD, 2002)

A new reasoning scheme for efficient redundancy addition and removal. - Chih-Wei Jim Chang; Ming-Fu Hsiao; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Fast postplacement optimization using functional symmetries. - Chih-Wei Jim Chang; Ming-Fu Hsiao; Bo Hu 006; Kai Wang 011; Malgorzata Marek-Sadowska; Chung-Kuan Cheng; Sao-Jie Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)