Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. - Chih-Wen Yang; Xin-Ru Lee; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2014)

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. - Xin-Ru Lee; Chih-Wen Yang; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2015)

An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes. - Xin-Ru Lee; Chih-Wen Yang; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 2.6mm2 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications. - Chi-Cheng Ju; Tsu-Ming Liu; Yung-Chang Chang; Chih-Ming Wang; Chia-Yun Cheng; Hue-Min Lin; Chun-Chia Chen; Min-Hao Chiu; Ping Chao; Ming-Long Wu; Meng-Jye Hu; Sheng-Jen Wang; et al. (ESSCIRC, 2016)

Late Breaking Results: Design Dependent Mega Cell Methodology for Area and Power Optimization. - Chien-Pang Lu; Iris Hui-Ru Jiang; Chih-Wen Yang (DAC, 2020)

Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines. - Chien-Pang Lu; Iris Hui-Ru Jiang; Chih-Wen Yang (ISPD, 2022)