Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product. - I-Cheng Lin; Chih-Yao Huang; Chuan-Jane Chao; Ming-Dou Ker (Microelectron. Reliab., 2003)

Design optimization of ESD protection and latchup prevention for a serial I/O IC. - Chih-Yao Huang; Wei-Fang Chen; Song-Yu Chuan; Fu-Chien Chiu; Jeng-Chou Tseng; I-Cheng Lin; Chuan-Jane Chao; Len-Yi Leu; Ming-Dou Ker (Microelectron. Reliab., 2004)