An SOC Test Integration Platform and Its Industrial Realization. - Kuo-Liang Cheng; Jing-Reng Huang; Chih-Wea Wang; Chih-Yen Lo; Li-Ming Denq; Chih-Tsun Huang; Shin-Wei Hung; Jye-Yuan Lee (ITC, 2004)

A network security processor design based on an integrated SOC design and test platform. - Chen-Hsing Wang; Chih-Yen Lo; Min-Sheng Lee; Jen-Chieh Yeh; Chih-Tsun Huang; Cheng-Wen Wu; Shi-Yu Huang (DAC, 2006)

STEAC: A Platform for Automatic SOC Test Integration. - Chih-Yen Lo; Chen-Hsing Wang; Kuo-Liang Cheng; Jing-Reng Huang; Chih-Wea Wang; Shin-Moe Wang; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Test Integration for SOC Supporting Very Low-Cost Testers. - Chun-Chuan Chi; Chih-Yen Lo; Te-Wen Ko; Cheng-Wen Wu (Asian Test Symposium, 2009)

SOC Test Architecture and Method for 3-D ICs. - Chih-Yen Lo; Yu-Tsao Hsing; Li-Ming Denq; Cheng-Wen Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A built-in self-test scheme for 3D RAMs. - Yun-Chao You; Che-Wei Chou; Jin-Fu Li 001; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (ITC, 2012)

An FPGA-based test platform for analyzing data retention time distribution of DRAMs. - Chih-Sheng Hou; Jin-Fu Li 001; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (VLSI-DAT, 2013)

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. - Yun-Chao You; Chih-Sheng Hou; Li-Jung Chang; Jin-Fu Li 001; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (VTS, 2013)

Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. - Kuan-Te Wu; Jin-Fu Li 001; Yun-Chao Yu; Chih-Sheng Hou; Chi-Chun Yang; Ding-Ming Kwai; Yung-Fa Chou; Chih-Yen Lo (ATS, 2014)

BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. - Yun-Chao You; Chi-Chun Yang; Jin-Fu Li 001; Chih-Yen Lo; Chao-Hsun Chen; Jenn-Shiang Lai; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (ATS, 2014)

A hybrid built-in self-test scheme for DRAMs. - Chi-Chun Yang; Jin-Fu Li 001; Yun-Chao Yu; Kuan-Te Wu; Chih-Yen Lo; Chao-Hsun Chen; Jenn-Shiang Lai; Ding-Ming Kwai; Yung-Fa Chou (VLSI-DAT, 2015)

Hierarchical Test Integration Methodology for 3-D ICs. - Che-Wei Chou; Jin-Fu Li 001; Yun-Chao Yu; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (IEEE Des. Test, 2015)

A Test Method for Finding Boundary Currents of 1T1R Memristor Memories. - Tzu-Ying Lin; Yong-Xiao Chen; Jin-Fu Li 001; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (ATS, 2016)

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. - Chih-Sheng Hou; Yong-Xiao Chen; Jin-Fu Li 001; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (ITC, 2016)

Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs. - Tsung-Fu Hsieh; Jin-Fu Li 001; Kuan-Te Wu; Jenn-Shiang Lai; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (ITC-Asia, 2017)

A channel-sharable built-in self-test scheme for multi-channel DRAMs. - Kuan-Te Wu; Jin-Fu Li 001; Chih-Yen Lo; Jenn-Shiang Lai; Ding-Ming Kwai; Yung-Fa Chou (ASP-DAC, 2018)

RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction. - Jia-Yun Hu; Kuan-Wei Hou; Chih-Yen Lo; Yung-Fa Chou; Cheng-Wen Wu (ITC-Asia, 2018)

Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method. - Tsung-Fu Hsieh; Jin-Fu Li 001; Jenn-Shiang Lai; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (ITC-Asia, 2020)