A 4b/cell NROM 1Gb Data-Storage Memory. - Yan Polansky; Avi Lavan; Ran Sahar; Oleg Dadashev; Yoram Betser; Guy Cohen; Eduardo Maayan; Boaz Eitan; Ful-Long Ni; Yen-Hui Joseph Ku; Chih-Yuan Lu; Tim Chang-Ting Chen; et al. (ISSCC, 2006)

Non-volatile Semiconductor Memory Technology in Nanotech Era. - Chih-Yuan Lu (MTDT, 2006)

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations. - Chun-Hsiung Hung; Meng-Fan Chang; Yih-Shan Yang; Yao-Jen Kuo; Tzu-Neng Lai; Shin-Jang Shen; Jo-Yu Hsu; Shuo-Nan Hung; Hang-Ting Lue; Yen-Hao Shih; Shih-Lin Huang; Ti-Wen Chen; et al. (IEEE J. Solid State Circuits, 2015)

Electrical method to localize the high-resistance of nanoscale CoSi2 word-line for OTP memories. - Ming-Yi Lee; T.-Y. Chang; W.-F. Hsueh; Li-Kuang Kuo; Ding-Jhang Lin; Yen-Hai Chao; U. J. Tzeng; Chih-Yuan Lu (IRPS, 2018)

Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory. - T. W. Lin; S. H. Ku; C. H. Cheng; C. W. Lee; Ijen Huang; Wen-Jer Tsai; T. C. Lu; W. P. Lu; K. C. Chen; Tahui Wang; Chih-Yuan Lu (IRPS, 2018)

Investigation of data pattern effects on nitride charge lateral migration in a charge trap flash memory by using a random telegraph signal method. - Y. H. Liu; H. Y. Lin; C. M. Jiang; Tahui Wang; W. J. Tsai; T. C. Lu; K. C. Chen; Chih-Yuan Lu (IRPS, 2018)

Modeling of Apparent Activation Energy and Lifetime Estimation for Retention of 3D SGVC Memory. - Wei-Hao Hsiao; Nian-Jia Wang; Ming-Yi Lee; Li-Kuang Kuo; Ding-Jhang Lin; Yen-Hai Chao; Chih-Yuan Lu (IRPS, 2019)

Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution. - Chieh Roger Lo; Teng-Hao Yeh; Wei-Chen Chen; Hang-Ting Lue; Keh-Chung Wang; Chih-Yuan Lu; Yao-Wen Chang; Yung-Hsiang Chen; Chu-Yung Liu (IRPS, 2020)

Introduction of Non-Volatile Computing In Memory (nvCIM) by 3D NAND Flash for Inference Accelerator of Deep Neural Network (DNN) and the Read Disturb Reliability Evaluation : (Invited Paper). - Hang-Ting Lue; Po-Kai Hsu; Keh-Chung Wang; Chih-Yuan Lu (IRPS, 2020)

Statistical Analysis of Bit-Errors Distribution for Reliability of 3-D NAND Flash Memories. - Nian-Jia Wang; Kuan-Yi Lee; Hsin-Yi Lin; Wei-Hao Hsiao; Ming-Yi Lee; Li-Kuang Kuo; Ding-Jhang Lin; Yen-Hai Chao; Chih-Yuan Lu (IRPS, 2020)

Write-In-Place Operation and It's Advantages to Upgrade the 3D AND-type Flash Memory Performances. - Hang-Ting Lue; Tzu-Hsuan Hsu; Cheng-Lin Sung; Teng-Hao Yeh; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2021)

First Study of P-Channel Vertical Split-Gate Flash Memory Device with Various Electron and Hole Injection Methods and Potential Future Possibility to Enable Functional Memory Circuits. - Cheng-Lin Sung; Hang-Ting Lue; Wei-Chen Chen; Tzu-Hsuan Hsu; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2021)

Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses. - Ming-Liang Wei; Hussam Amrouch; Cheng-Lin Sung; Hang-Ting Lue; Chia-Lin Yang; Keh-Chung Wang; Chih-Yuan Lu (IRPS, 2021)

Design of Computing-in-Memory (CIM) with Vertical Split-Gate Flash Memory for Deep Neural Network (DNN) Inference Accelerator. - Hang-Ting Lue; Han-Wen Hu; Tzu-Hsuan Hsu; Po-Kai Hsu; Keh-Chung Wang; Chih-Yuan Lu (ISCAS, 2021)

NOR Flash-based Multilevel In-Memory-Searching Architecture for Approximate Computing. - Yu-Hsuan Lin; Po-Hao Tseng; Feng-Min Lee; Ming-Hsiu Lee; Chih-Chang Hsieh; Dai-Ying Lee; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2022)

First Experimental Study of Floating-Body Cell Transient Reliability Characteristics of Both N- and P-Channel Vertical Gate-All-Around Devices with Split-Gate Structures. - Cheng-Lin Sung; Sheng-Ting Fan; Hang-Ting Lue; Wei-Chen Chen; Pei-Ying Du; Teng-Hao Yeh; Keh-Chung Wang; Chih-Yuan Lu (IRPS, 2022)

A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI Devices. - Han-Wen Hu; Wei-Chen Wang 002; Chung Kuang Chen; Yung-Chun Lee; Bo-Rong Lin; Huai-Mu Wang; Yen-Po Lin; Yu-Chao Lin; Chih-Chang Hsieh; Chia-Ming Hu; Yi-Ting Lai; Han-Sung Chen; et al. (ISSCC, 2022)

ICE: An Intelligent Cognition Engine with 3D NAND-based In-Memory Computing for Vector Similarity Search Acceleration. - Han-Wen Hu; Wei-Chen Wang 002; Yuan-Hao Chang 001; Yung-Chun Lee; Bo-Rong Lin; Huai-Mu Wang; Yen-Po Lin; Yu-Ming Huang; Chong-Ying Lee; Tzu-Hsiang Su; Chih-Chang Hsieh; Chia-Ming Hu; et al. (MICRO, 2022)

In-Memory Approximate Computing Architecture Based on 3D-NAND Flash Memories. - Po-Hao Tseng; Yu-Hsuan Lin; Feng-Ming Lee; Tian-Cig Bo; Yung-Chun Li; Ming-Hsiu Lee; Kuang-Yeu Hsieh; Keh-Chung Wang; Chih-Yuan Lu (VLSI Technology and Circuits, 2022)

A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device. - Wei-Chen Chen; Hang-Ting Lue; Tzu-Hsuan Hsu; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2023)

SLC and MLC In-Memory-Approximate-Search Solutions in Commercial 48-layer and 96-layer 3D-NAND Flash Memories. - Po-Hao Tseng; Tian-Cig Bo; Yu-Hsuan Lin; Yu-Chao Lin; Jhe-Yi Liao; Feng-Ming Lee; Yu-Yu Lin; Ming-Hsiu Lee; Kuang-Yeu Hsieh; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2023)

Chip Demonstration of a High-Density (43Gb) and High-Search-Bandwidth (300Gb/s) 3D NAND Based In-Memory Search Accelerator for Ternary Content Addressable Memory (TCAM) and Proximity Search of Hamming Distance. - Chih-Chang Hsieh; Hang-Ting Lue; Yung-Chun Li; Shuo-Nan Hung; Chun-Hsiung Hung; Keh-Chung Wang; Chih-Yuan Lu (VLSI Technology and Circuits, 2023)

Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL's and Vertical BL for Better Cell Size Scaling and Array Selection. - Wei-Chen Chen; Hang-Ting Lue; Ming-Hung Wu; Yu-Tang Lin; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2024)

Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling 2-tier Stacked 4F2 DRAM Below Equivalent 10nm Node. - Hang-Ting Lue; Wei-Chen Chen; Yu-Tang Lin; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2024)

3D-NAND based Filtering Cube with High Resolution 2D Query and Tunable Feature Length for Computational SSD. - Po-Hao Tseng; Shao-Yu Fang; Yu-Hsuan Lin; Feng-Ming Lee; Jhe-Yi Liao; Yu-Yu Lin; Ming-Hsiu Lee; Kuang-Yeu Hsieh; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2024)

Charge Loss Improvement in 3D Flash Memory by Molecular Oxidation of Tunneling Oxide. - Pei-Ci Jhang; Chi-Pin Lu; Jung-Yu Shieh; Ling-Wu Yang; Tahone Yang; Kuang-Chao Chen; Hang-Ting Lue; Pei-Ying Du; Chih-Yuan Lu (IRPS, 2024)

Reliability Assessment for an In-3D-NAND Approximate Searching Solution. - Po-Hao Tseng; Yu-Hsuan Lin; Feng-Min Lee; Tian-Cig Bo; Ming-Hsiu Lee; Kuang-Yeu Hsieh; Keh-Chung Wang; Chih-Yuan Lu (IRPS, 2024)

Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs. - Feng-Min Lee; Po-Hao Tseng; Yu-Yu Lin; Yu-Hsuan Lin; Wei-Lun Weng; Nei-Chih Lin; Po-Jung Sung; Chien-Ting Wu; Chih-Chao Yang; Wen-Fa Wu; Chang-Hong Shen; Tuo-Hung Hou; et al. (VLSI Technology and Circuits, 2024)

Utilizing 2T SONOS Cell Characteristics for L2/Euclidean Distance Computing - From Unit Cell to Array Operations. - Yu-Hsuan Lin; Po-Hao Tseng; Ming-Hsiu Lee; Yu-Yu Lin; Feng-Min Lee; Dai-Ying Lee; Pei-Ying Du; Chih-Chieh Lin; Teng-Hao Yeh; Kuang-Yeu Hsieh; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2025)

A Novel 3D Stacked Vertical-Channel High-Voltage Peripheral Transistor for Largely Scaled the WL Driver Circuit of 1000-layer 3D NAND Flash. - Teng-Hao Yeh; Hang-Ting Lue; Wei-Chen Chen; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2025)