LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives. - Chao Sun 001; Ayumi Soga; Chihiro Matsui; Asuka Arakawa; Ken Takeuchi (IEEE Trans. Very Large Scale Integr. Syst., 2016)

22% Higher performance, 2x SCM write endurance heterogeneous storage with dual storage class memory and NAND flash. - Chihiro Matsui; Ken Takeuchi (ESSDERC, 2017)

Workload-Based Co-Design of Non-Volatile Cache Algorithm and Storage Class Memory Specifications for Storage Class Memory/NAND Flash Hybrid SSDs. - Tomoaki Yamada; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2017)

Design of Hybrid SSDs With Storage Class Memory and NAND Flash Memory. - Chihiro Matsui; Chao Sun 001; Ken Takeuchi (Proc. IEEE, 2017)

Write Order-Based Garbage Collection Scheme for an LBA Scrambler Integrated SSD. - Chihiro Matsui; Asuka Arakawa; Chao Sun 001; Ken Takeuchi (IEEE Trans. Very Large Scale Integr. Syst., 2017)

20% System-performance Gain of 3D Charge-trap TLC NAND Flash over 2D Floating-gate MLC NAND Flash for SCM/NAND Flash Hybrid SSD. - Mamoru Fukuchi; Yukiya Sakaki; Chihiro Matsui; Ken Takeuchi (ISCAS, 2018)

3ASCA: Application-Aware Autonomous SCM Capacity Adjustment for SCM and NAND Flash Pooled Storage. - Chihiro Matsui; Ken Takeuchi (ISCAS, 2018)

Maximizing Peformance/cost Figure of Merit of Storage-type SCM based SSD by Adding Small Capacity of Memory-type SCM. - Reika Kinoshita; Chihiro Matsui; Shinpei Matsuda; Yutaka Adachi; Ken Takeuchi (NVMTS, 2018)

Periodic Data Eviction Algorithm of SCM/NAND Flash Hybrid SSD with SCM Retention Time Constraint Capabilities at Extremely High Temperature. - Atsuya Suzuki; Chihiro Matsui; Ken Takeuchi (NVMTS, 2018)

Double asymmetric-latency storage class memories (SCMs) for fast-write SCM, fast-read SCM & NAND flash hybrid SSDs. - Yutaka Adachi; Chihiro Matsui; Ken Takeuchi (VLSI-DAT, 2018)

Analysis of SCM-Based SSD Performance in Consideration of SCM Access Unit Size, Write/Read Latencies and Application Request Size. - Hirofumi Takishita; Yutaka Adachi; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2018)

Reliability Analysis of Scaled NAND Flash Memory Based SSDs with Real Workload Characteristics by Using Real Usage-Based Precise Reliability Test. - Yusuke Yamaga; Chihiro Matsui; Yukiya Sakaki; Ken Takeuchi (IEICE Trans. Electron., 2018)

Design of heterogeneously-integrated memory system with storage class memories and NAND flash memories. - Chihiro Matsui; Ken Takeuchi (ASP-DAC, 2019)

Self-Determining Resource Control in Multi-Tenant Data Center Storage with Future NV Memories. - Chihiro Matsui; Ken Takeuchi (ISCAS, 2019)

Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage. - Chihiro Matsui; Ken Takeuchi (Integr., 2019)

Dynamic Adjustment of Storage Class Memory Capacity in Memory-Resource Disaggregated Hybrid Storage With SCM and NAND Flash Memory. - Chihiro Matsui; Ken Takeuchi (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System Performance. - Reika Kinoshita; Chihiro Matsui; Atsuya Suzuki; Shouhei Fukuyama; Ken Takeuchi (ASP-DAC, 2020)

Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers. - Yoshiki Kakuta; Reika Kinoshita; Hiroshi Kinoshita; Chihiro Matsui; Ken Takeuchi (VLSI-DAT, 2020)

System Performance Comparison of 3D Charge-Trap TLC NAND Flash and 2D Floating-Gate MLC NAND Flash Based SSDs. - Mamoru Fukuchi; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2020)

Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs). - Yoshiki Takai; Mamoru Fukuchi; Chihiro Matsui; Reika Kinoshita; Ken Takeuchi (IEICE Trans. Electron., 2020)

Simulated Annealing Algorithm & ReRAM Device Co-optimization for Computation-in-Memory. - Kenta Taoka; Naoko Misawa; Shunsuke Koshino; Chihiro Matsui; Ken Takeuchi (IMW, 2021)

BER Evaluation System Considering Device Characteristics of TLC and QLC NAND Flash Memories in Hybrid SSDs with Real Storage Workloads. - Mamoru Fukuchi; Shun Suzuki; Kyosuke Maeda; Chihiro Matsui; Ken Takeuchi (ISCAS, 2021)

Energy-Efficient Reliable HZO FeFET Computation-in-Memory with Local Multiply & Global Accumulate Array for Source-Follower & Charge-Sharing Voltage Sensing. - Chihiro Matsui; Kasidit Toprasertpong; Shinichi Takagi; Ken Takeuchi (VLSI Circuits, 2021)

Non-volatile Memory Application to Quantum Error Correction with Non-uniformly Quantized CiM. - Yuya Ichikawa; Akira Goda; Chihiro Matsui; Ken Takeuchi (IMW, 2022)

Edge Retraining of FeFET LM-GA CiM for Write Variation & Reliability Error Compensation. - Shinsei Yoshikiyo; Naoko Misawa; Kasidit Toprasertpong; Shinichi Takagi; Chihiro Matsui; Ken Takeuchi (IMW, 2022)

Versatile FeFET Voltage-sensing Analog CiM for Fast & Small-area Hyperdimensional Computing. - Chihiro Matsui; Eitaro Kobayashi; Kasidit Toprasertpong; Shinichi Takagi; Ken Takeuchi (ISCAS, 2022)

Domain Specific ReRAM Computation-in-Memory Design Considering Bit Precision and Memory Errors for Simulated Annealing. - Naoko Misawa; Kenta Taoka; Chihiro Matsui; Ken Takeuchi (ISCAS, 2022)

Edge Computation-in-Memory for In-situ Class-incremental Learning with Knowledge Distillation. - Shinsei Yoshikiyo; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (ISCAS, 2022)

LIORAT: NN Layer I/O Range Training for Area/Energy-Efficient Low-Bit A/D Conversion System Design in Error-Tolerant Computation-in-Memory. - Ayumu Yamada; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (ICCAD, 2023)

Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance. - Takuto Nishimura; Yuya Ichikawa; Akira Goda; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (IMW, 2023)

ReRAM CiM Fluctuation Pattern Classification by CNN Trained on Artificially Created Dataset. - Ayumu Yamada; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (IRPS, 2023)

Heterogeneous Integration of Precise and Approximate Storage for Error-Tolerant Workloads. - Chihiro Matsui; Ken Takeuchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Write Variation & Reliability Error Compensation by Layer-Wise Tunable Retraining of Edge FeFET LM-GA CiM. - Shinsei Yoshikiyo; Naoko Misawa; Kasidit Toprasertpong; Shinichi Takagi; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2023)

Embedded Transformer Hetero-CiM: SRAM CiM for 4b Read/Write-MAC Self-attention and MLC ReRAM CiM for 6b Read-MAC Linear&FC Layers. - Naoko Misawa; Tao Wang; Chihiro Matsui; Ken Takeuchi (IMW, 2024)

REM-CiM: Attentional RGB-Event Fusion Multi-Modal Analog CiM for Area/Energy-Efficient Edge Object Detection during Both Day and Night. - Yuya Ichikawa; Ayumu Yamada; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2024)

3D Parallel ReRAM Computation-in-Memory for Hyperdimensional Computing. - Fuyuki Kihara; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2024)

Comprehensive Analysis of Read Fluctuations in ReRAM CiM by Using Fluctuation Pattern Classifier. - Ayumu Yamada; Zhiyuan Huang; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2024)

FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing. - Chihiro Matsui; Kasidit Toprasertpong; Shinichi Takagi; Ken Takeuchi (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Transformer Hetero-CiM: Heterogeneous Integration of ReRAM CiM and SRAM CiM for Vision Transformer at Edge Devices. - Naoko Misawa; Tao Wang 126; Chihiro Matsui; Ken Takeuchi (ASP-DAC, 2025)

Hybrid ReRAM-NMC & SRAM-CiM Matrix Multiplication for Large Language Model. - Tao Wang; Daqi Lin; Kenshin Yamauchi; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (COOL CHIPS, 2025)

Bayesian Neural Network Realization by Random Telegraph Noise in 40nm TaOX ReRAM CiM. - Junnosuke Furukawa; Koki Shibata; Kenshin Yamauchi; Naoko Misawa; Satoshi Awamura; Chihiro Matsui; Ken Takeuchi (IMW, 2025)

Conductance Variation-Assisted Adversarial Attack Robustness on 40nm TaOx-based ReRAM CiM. - Kenshin Yamauchi; Naoko Misawa; Satoshi Awamura; Masahiro Morimoto; Chihiro Matsui; Ken Takeuchi (IRPS, 2025)

Read Voltage Dependency of Random Telegraph Noise in the Intermediate State of TaOx-based ReRAM. - Kenshin Yamauchi; Naoko Misawa; Hisashi Shima; Yasuhisa Naitoh; Hiroyuki Akinaga; Chihiro Matsui; Ken Takeuchi (IRPS, 2025)

VaLI: Variability-aware Fine-tuning with Low-rank Adapter and Iterative Training for ReRAM Computation-in-Memory. - Tao Wang; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (ISCAS, 2025)

RGB-Event Multi-Modal NV-CiM to Detect Object by Mapping-Oriented Enhanced-Feature Pyramid Network with Mapping-Aware Group Convolution. - Yuya Ichikawa; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation. - Fuyuki Kihara; Seiji Uenohara; Satoshi Awamura; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (CoRR, 2025)