GPMB - software pipelining branch-intensive loops. - Zhizhong Tang; Gang Chen; Chihong Zhang; Yingwei Zhang; Bogong Su; Stanley Habib (MICRO, 1993)

URPR-1: A single-chip VLIW architecture. - Bogong Su; Jian Wang 046; Zhizhong Tang; Chihong Zhang; Wei Zhao (Microprocess. Microprogramming, 1993)

A New Architecture For Branch-Intensive Loops. - Zhizhong Tang; Chihong Zhang; Sifei Lvand; Tao Yu (APDC, 1997)

Control Mechanism for Software Pipelining on Nested Loop. - Tao Yu; Zhizhong Tang; Chihong Zhang; Jun Luo (APDC, 1997)

An Improvement on Data Dependence Analysis Supporting Software Pipelining Technique. - Chihong Zhang; Zhizhong Tang (APDC, 1997)

Efficient State-Diagram Construction Methods for Software Pipelining. - Chihong Zhang; Ramaswamy Govindarajan; Sean Ryan; Guang R. Gao (CC, 1999)

Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors. - Ramaswamy Govindarajan; Chihong Zhang; Guang R. Gao (LCPC, 1999)

Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs. - Ramaswamy Govindarajan; Hongbo Yang; Chihong Zhang; José Nelson Amaral; Guang R. Gao (IPDPS, 2001)

Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures. - Ramaswamy Govindarajan; Hongbo Yang; José Nelson Amaral; Chihong Zhang; Guang R. Gao (IEEE Trans. Computers, 2003)