New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering. - Chika Tanaka; Keiji Ikeda; Masumi Saitoh (ESSDERC, 2015)

BSIM4 parameter extraction for tri-gate Si nanowire transistors. - Chika Tanaka; Masumi Saitoh; Kensuke Ota; Takayuki Ishikawa; Toshinori Numata (Microelectron. J., 2016)

Charge-based Neuromorphic Cell by InGaZnO Transistor and Implementation of Simple Scheme Spike-Timing-Dependent Plasticity. - Chika Tanaka; Keiji Ikeda (ISCAS, 2018)

SPICE simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation. - Tetsufumi Tanamoto; Chika Tanaka; Satoshi Takaya; Masato Koyama (IEICE Electron. Express, 2018)

SPICE simulation of 32-kHz crystal-oscillator operation based on Si tunnel FET. - Tetsufumi Tanamoto; Chika Tanaka; Shinichi Takagi (IEICE Electron. Express, 2020)

Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic Operation. - Dondee Navarro; Shin Taniguchi; Chika Tanaka; Kazutoshi Kobayashi; Takashi Sato 001; Michihiro Shintani (ASP-DAC, 2025)

Detection of Lung Regions from LDCT Images and 3D Image Registration Using FFD. - Chika Tanaka; Tohru Kamiya; Takashi Terasawa; Takatoshi Aoki (ICBEA, 2025)