Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine. - Hideki Ando; Chikako Nakanishi; Hirohisa Machida; Tetsuya Hara; Satoru Kishida; Masao Nakaya (ICCD, 1993)

Unconstrained Speculative Execution with Predicated State Buffering. - Hideki Ando; Chikako Nakanishi; Tetsuya Hara; Masao Nakaya (ISCA, 1995)

Code scheduling on a superscalar processor: SARCH. - Chikako Nakanishi; Hideki Ando; Hirohisa Machida; Masao Nakaya (Syst. Comput. Jpn., 1995)

Performance Comparison of ILP Machines with Cycle Time Evaluation. - Tetsuya Hara; Hideki Ando; Chikako Nakanishi; Masao Nakaya (ISCA, 1996)

Software pipelining with path selection. - Chikako Nakanishi; Hideki Ando; Tetsuya Hara; Masao Nakaya (Syst. Comput. Jpn., 1998)

FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature. - Yuri Nishizumi; Go Matsukawa; Koichi Kajihara; Taisuke Kodama; Shintaro Izumi; Hiroshi Kawaguchi 001; Chikako Nakanishi; Toshio Goto; Takeo Kato; Masahiko Yoshimoto (SiPS, 2017)

A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video. - Go Matsukawa; Taisuke Kodama; Yuri Nishizumi; Koichi Kajihara; Chikako Nakanishi; Shintaro Izumi; Hiroshi Kawaguchi 001; Toshio Goto; Takeo Kato; Masahiko Yoshimoto (IEICE Electron. Express, 2017)

A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668]. - Go Matsukawa; Taisuke Kodama; Yuri Nishizumi; Koichi Kajihara; Chikako Nakanishi; Shintaro Izumi; Hiroshi Kawaguchi 001; Toshio Goto; Takeo Kato; Masahiko Yoshimoto (IEICE Electron. Express, 2018)