Corrections to "VLSI Design of Diminished-One Modulo 2n + 1 Adder Using Circular Carry Selection" [Sep 08 897-901]. - Tso-Bing Juang; Ming-Yu Tsai; Chin-Chieh Chiu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Improved Area-Efficient Weighted Modulo 2n + 1 Adder Design With Simple Correction Schemes. - Tso-Bing Juang; Chin-Chieh Chiu; Ming-Yu Tsai (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Low-cost concurrent error detection schemes for logarithmic converters. - Tso-Bing Juang; Ying-Ren Lee; Chin-Chieh Chiu (ISOCC, 2016)