Low-Complexity Bit-Parallel Systolic Multipliers over GF(2m). - Chiou-Yng Lee; Chin-Chin Chen; Yuan-Ho Chen; Erl-Huei Lu (SMC, 2006)

Combined circuit architecture for computing normal basis and montgomery multiplications over GF(2m). - Chin-Chin Chen; Chiou-Yng Lee; Erl-Huei Lu (Mobility Conference, 2008)

Scalable and Systolic Montgomery Multipliers over GF(2m). - Chin-Chin Chen; Chiou-Yng Lee; Erl-Huei Lu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)