The new architecture of radix-4 Chinese abacus adder. - Shu-Chung Yi; Kun-Tse Lee; Jin-Jia Chen; Chien-Hung Lin; Chuen-Ching Wang; Chin-Fa Hsieh; Chih-Yung Lu (ISMVL, 2006)

A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes. - Chin-Fa Hsieh; Tsung-Han Tsai; Neng-Jye Hsu; Chih-Hung Lai (JCIS, 2006)

A Cost-Effective Noise-Reduction Filtering Structure Based on Unsymmetrical Working Windows. - Chin-Fa Hsieh; Tsung-Han Tsai; Shu-Ping Chang; Tai-An Shan (IIH-MSP, 2007)

A Novel Efficient VLSI Architecture of 2-D Discrete Wavelet Transform. - Chin-Fa Hsieh; Tsung-Han Tsai 001; Chih-Hung Lai; Tai-An Shan (IIH-MSP, 2008)

An arithmetic controller design for numerical control. - Shu-Chung Yi; Chin-Fa Hsieh (Comput. Electr. Eng., 2013)

A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design. - Mao-Hsu Yen; Chu Yu; Horng-Ru Liao; Chin-Fa Hsieh (VLSI Design, 2013)

A SoC Integrating ADC and 2DDWT for Video/Image Processing. - Chin-Fa Hsieh; Tsung-Han Tsai 001; Shu-Chung Yi (IEICE Trans. Electron., 2016)

Automatic Vehicle License Plate Recognition Based on YOLO v4 for Smart Parking Management System. - Chin-Fa Hsieh; Cheng-Zhi Lin; Zheng-Zhe Li; Cheng-Hsiu Cho (GCCE, 2022)

Implementation of a Smart Checkout System Based on Face Recognition Using YOLO v3-tiny. - Chin-Fa Hsieh; Pin-Hong Liu; Jai-Xuan Lai; Shih-Hao Sun (GCCE, 2022)

High Performance Architecture of a Graphics Accelerator. - Chin-Fa Hsieh; Li-Chi Chen; Zhe-Hao Lin (ICCE-TW, 2022)