An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay. - Chin Hau Hoo; Akash Kumar 001 (FPL, 2012)

A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm. - Chin Hau Hoo; Yajun Ha; Akash Kumar 001 (FPL, 2013)

Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology. - Wenfeng Zhao; Yajun Ha; Chin Hau Hoo; Anastacia B. Alvarez (ISLPED, 2013)

ParaLaR: A parallel FPGA router based on Lagrangian relaxation. - Chin Hau Hoo; Akash Kumar 001; Yajun Ha (FPL, 2015)

ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning. - Chin Hau Hoo; Yajun Ha; Akash Kumar 001 (FPL, 2016)

ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding. - Chin Hau Hoo; Akash Kumar 001 (FCCM, 2017)

ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling. - Chin Hau Hoo; Akash Kumar 001 (FPGA, 2018)