A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology. - Wei-Chih Chen; Chien-Chun Tsai; Chih-Hsien Chang; Yung-Chow Peng; Fu-Lung Hsueh; Tsung-Hsin Yu; Jinn-Yeh Chien; Wen-Hung Huang; Chi-Chang Lu; Mu-Shan Lin; Chin-Ming Fu; Shu-Chun Yang; et al. (CICC, 2010)

A sub-micron CMOS-based ISFET array for biomolecular sensing. - Yu-Han Sun; Guan-Yin Chen; Chih-Ting Lin; Jui-Cheng Huang; Yu-Jie Huang; Chin-Hua Wen (NEMS, 2016)

A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS. - Wei-Chih Chen; Chin-Hua Wen; Chin-Ming Fu; Tsung-Hsien Tsai; Yu-Chi Chen; Wen-Hung Huang; Chien-Chun Tsai; Alvin Leng Sun Loke; C. H. Kenny (VLSI Circuits, 2020)

A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Tze-Chiang Huang; Wen-Hung Huang; Kate Huang; Yu-Chi Chen; Alex Liu; Yu-Jie Huang; Jimmy Wang; Shu-Chun Yang; Nai-Chen Cheng 001; et al. (VLSI Technology and Circuits, 2024)

36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Wei-Chih Chen; Wen-Hung Huang; Yu-Chi Chen; Yu-Jie Huang; Alan J. Drake; Chin-Hua Wen; Paul Ranucci; Hsin-Hung Kuo; Aidong Yin; et al. (ISSCC, 2025)