A fast readout circuit for an organic vertical nano-junction sensor. - Trong-Hieu Tran; Paul C.-P. Chao 001; Chin-I Su; Hsiao-Wen Zan (IEEE SENSORS, 2016)

Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window. - Chien-An Lai; Chung-Cheng Chou; Chi-Hsiang Weng; Zheng-Jun Lin; Pei-Ling Tseng; Chien-Fan Wang; Chih-Chen Wang; Chin-I Su; Wei-Chi Chen; Yu-Cheng Lin; Tong-Chern Ong; Chi Chang; et al. (A-SSCC, 2018)

A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range. - Chung-Cheng Chou; Zheng-Jun Lin; Chien-An Lai; Chin-I Su; Pei-Ling Tseng; Wei-Chi Chen; Wu-Chin Tsai; Wen-Ting Chu; Tong-Chern Ong; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Circuits, 2020)

An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM. - Zhehong Wang; Ziyun Li; Li Xu 006; Qing Dong 001; Chin-I Su; Wen-Ting Chu; George Tsou; Yu-Der Chih; Tsung-Yung Jonathan Chang; Dennis Sylvester; Hun-Seok Kim; David T. Blaauw (VLSI Circuits, 2020)

A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices. - Cheng-Xin Xue; Je-Min Hung; Hui-Yao Kao; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Peng Chen; Ta-Wei Liu; Chuan-Jia Jhang; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; et al. (ISSCC, 2021)

RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator. - Ziyun Li; Zhehong Wang; Li Xu 006; Qing Dong 001; Bowen Liu 001; Chin-I Su; Wen-Ting Chu; George Tsou; Yu-Der Chih; Tsung-Yung Jonathan Chang; Dennis Sylvester; Hun-Seok Kim; et al. (IEEE J. Solid State Circuits, 2021)

An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices. - Je-Min Hung; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Tai-Hao Wen; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; et al. (ISSCC, 2022)

A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices. - Tai-Hao Wen; Je-Min Hung; Hung-Hsi Hsu; Yuan Wu 009; Fu-Chun Chang; Chung-Yuan Li; Chih-Han Chien; Chin-I Su; Win-San Khwa; Jui-Jen Wu; Chung-Chuan Lo; Ren-Shuo Liu; et al. (VLSI Technology and Circuits, 2023)

8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices. - Je-Min Hung; Tai-Hao Wen; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; et al. (IEEE J. Solid State Circuits, 2023)