Cliff C. N. Sze

IPSJ Trans. Syst. LSI Des. Methodol., 2017

Fast and Highly Scalable Bayesian MDP on a GPU Platform.

[BibT_eX]

[DOI]

Proceedings of the 8th ACM International Conference on Bioinformatics, 2017

2016

Challenges of cell selection algorithms in industrial high performance microprocessor designs.

[BibT_eX]

[DOI]

Tiago Reimann

Ricardo Reis

Integr., 2016

Cell Selection for High-Performance Designs in an Industrial Design Flow.

[BibT_eX]

[DOI]

Tiago J. Reimann

Ricardo Reis

Proceedings of the 2016 on International Symposium on Physical Design, 2016

GPU acceleration for Bayesian control of Markovian genetic regulatory networks.

[BibT_eX]

[DOI]

Mohammadmahdi R. Yousefi

Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016

2015

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes.

[BibT_eX]

[DOI]

Azadeh Davoodi

Muhammet Mustafa Ozdal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Gate sizing and threshold voltage assignment for high performance microprocessor designs.

[BibT_eX]

[DOI]

Tiago Reimann

Ricardo Reis

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Techniques for scalable and effective routability evaluation.

[BibT_eX]

[DOI]

Yaoguang Wei

ACM Trans. Design Autom. Electr. Syst., 2014

Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design.

[BibT_eX]

[DOI]

Cheng-Kok Koh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Pacman: driving nonuniform clock grid loads for low-skew robust clock network.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

2013

ISPD 2013 expert designer/user session (eds).

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

Clock power minimization using structured latch templates and decision tree induction.

[BibT_eX]

[DOI]

Samuel I. Ward

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Hardware Acceleration of an Efficient and Accurate Proton Therapy Monte Carlo.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computational Science, 2013

CATALYST: planning layer directives for effective design closure.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Routing congestion estimation with real design constraints.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Postgrid Clock Routing for High Performance Microprocessor Designs.

[BibT_eX]

[DOI]

Haitong Tian

Wai-Chung Tang

Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Placement: Hot or Not?

[BibT_eX]

[DOI]

Samuel I. Ward

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

WRIP: logic restructuring techniques for wirelength-driven incremental placement.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

GLARE: global and local wiring aware routability evaluation.

[BibT_eX]

[DOI]

Yaoguang Wei

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

The DAC 2012 routability-driven placement contest and benchmark suite.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing.

[BibT_eX]

[DOI]

Nancy Y. Zhou

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Shedding Physical Synthesis Area Bloat.

[BibT_eX]

[DOI]

VLSI Design, 2011

Physical Synthesis with Clock-Network Optimization for Large Systems on Chips.

[BibT_eX]

[DOI]

Gi-Joon Nam

Igor L. Markov

IEEE Micro, 2011

Design methodology for the IBM POWER7 microprocessor.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2011

Quantifying academic placer performance on custom designs.

[BibT_eX]

[DOI]

Earl E. Swartzlander Jr.

Proceedings of the 2011 International Symposium on Physical Design, 2011

The ISPD-2011 routability-driven placement contest and benchmark suite.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Physical Design, 2011

Grid-to-ports clock routing for high performance microprocessor designs.

[BibT_eX]

[DOI]

Haitong Tian

Wai-Chung Tang

Evangeline F. Y. Young

Proceedings of the 2011 International Symposium on Physical Design, 2011

The future of clock network synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Wire synthesizable global routing for timing closure.

[BibT_eX]

[DOI]

Michael D. Moffitt

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

ISPD 2010 high performance clock network synthesis contest: benchmark suite and results.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Physical Design, 2010

Ultra-fast interconnect driven cell cloning for minimizing critical path delay.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Physical Design, 2010

A methodology for propagating design tolerances to shape tolerances for use in manufacturing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Ispd2009 clock network synthesis contest.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Physical Design, 2009

2008

Buffering in the Layout Environment.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Timing-Driven Interconnect Synthesis.

[BibT_eX]

[DOI]

Gabriel Robins

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

The ISPD global routing benchmark suite.

[BibT_eX]

[DOI]

Gi-Joon Nam

Mehmet Can Yildiz

Proceedings of the 2008 International Symposium on Physical Design, 2008

Pyramids: an efficient computational geometry-based approach for timing-driven placement.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007

Algorithms for the scaling toward nanometer VLSI physical synthesis.

[BibT_eX]

[DOI]

PhD thesis, 2007

Path-Based Buffer Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fast Algorithms for Slew-Constrained Minimum Cost Buffering.

[BibT_eX]

[DOI]

Shiyan Hu

Shrirang K. Karandikar

Zhuo Li

Weiping Shi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Techniques for Fast Physical Synthesis.

[BibT_eX]

[DOI]

Shrirang K. Karandikar

Proc. IEEE, 2007

The nuts and bolts of physical synthesis.

[BibT_eX]

[DOI]

Shrirang K. Karandikar

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

2006

Accurate estimation of global buffer delay within a floorplan.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Integrated placement and skew optimization for rotary clocking.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Timing-driven Steiner trees are (practically) free.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Navigating Register Placement for Low Power Clock Network Design.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Navigating registers in placement for clock network minimization.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Skew scheduling and clock routing for improved tolerance to process variations.

[BibT_eX]

[DOI]

Ganesh Venkataraman

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Making fast buffer insertion even faster via approximation techniques.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Multilevel circuit clustering for delay minimization.

[BibT_eX]

[DOI]

Li-C. Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Porosity-aware buffered Steiner tree construction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A place and route aware buffered Steiner tree construction.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Optimal circuit clustering for delay minimization under a more general delay model.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Performance-driven multi-level clustering for combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Accelerating Logic Rewiring Using Implication Analysis Tree.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Multi-Level Circuit Clustering for Delay Minimization.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Optimal circuit clustering with variable interconnect delay.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

Improved alternative wiring scheme applying dominator relationship.

[BibT_eX]

[DOI]