An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network. - I-Chen Wu; Po-Tsang Huang; Chin-Yang Lo; Wei Hwang (AICAS, 2019)

Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs. - Chin-Yang Lo; Po-Tsang Huang; Wei Hwang (AICAS, 2020)

Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks. - Po-Tsang Huang; I-Chen Wu; Chin-Yang Lo; Wei Hwang (IEEE Open J. Circuits Syst., 2021)