Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology. - Guan-Sing Chen; Chin-Yang Wu; Chen-Lun Lin; Hao-Wei Hung; Jri Lee (A-SSCC, 2014)

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology. - Ping-Chuan Chiang; Jhih-Yu Jiang; Hao-Wei Hung; Chin-Yang Wu; Gaun-Sing Chen; Jri Lee (IEEE J. Solid State Circuits, 2015)

A 0.031mm2, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS. - Chin-Yang Wu; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (CICC, 2017)

A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS. - Ting-Kuei Kuan; Chin-Yang Wu; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (VLSI Circuits, 2018)