An all-digital phase-locked loop for high-speed clock generation. - Ching-Che Chung; Chen-Yi Lee (IEEE J. Solid State Circuits, 2003)

A new DLL-based approach for all-digital multiphase clock generation. - Ching-Che Chung; Chen-Yi Lee (IEEE J. Solid State Circuits, 2004)

An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications. - Pao-Lung Chen; Ching-Che Chung; Chen-Yi Lee (ISCAS (5), 2005)

A portable digitally controlled oscillator using novel varactors. - Pao-Lung Chen; Ching-Che Chung; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (APCCAS, 2006)

Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications. - Tsu-Ming Liu; Ching-Che Chung; Chen-Yi Lee; Ting-An Lin; Sheng-Zen Wang (DAC, 2006)

A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications. - Pao-Lung Chen; Ching-Che Chung; Jyh-Neng Yang; Chen-Yi Lee (IEEE J. Solid State Circuits, 2006)

A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications. - Jui-Yuan Yu; Ching-Che Chung; Wan-Chun Liao; Chen-Yi Lee (ISSCC, 2007)

An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems. - Jui-Yuan Yu; Juinn-Ting Chen; Mei-Hui Yang; Ching-Che Chung; Chen-Yi Lee (SoCC, 2007)

An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

An all digital spread spectrum clock generator with programmable spread ratio for SoC applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (APCCAS, 2008)

A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems. - Jui-Yuan Yu; Ching-Che Chung; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

An all-digital smart temperature sensor with auto-calibration in 65nm CMOS technology. - Ching-Che Chung; Cheng-Ruei Yang (ISCAS, 2010)

Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (IEICE Electron. Express, 2010)

A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology. - Ching-Che Chung; Duo Sheng; Chia-Lin Chang (IEICE Electron. Express, 2011)

A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology. - Ching-Che Chung; Duo Sheng; Sung-En Shen (IEICE Electron. Express, 2011)

A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology. - Ching-Che Chung; Chiun-Yao Ko (IEEE J. Solid State Circuits, 2011)

Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology. - Ching-Che Chung; Chiun-Yao Ko; Sung-En Shen (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

An Autocalibrated All-Digital Temperature Sensor for On-Chip Thermal Monitoring. - Ching-Che Chung; Cheng-Ruei Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications. - Duo Sheng; Ching-Che Chung; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications. - Ching-Che Chung; Jui-Yuan Yu; Shiou-Ru Jang; Chen-Yi Lee (J. Signal Process. Syst., 2011)

A low-complexity high-performance wear-leveling algorithm for flash memory system design. - Ching-Che Chung; Ning-Mi Hsueh (APCCAS, 2012)

A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology. - Ching-Che Chung; Duo Sheng; Wei-Da Ho (VLSI-DAT, 2012)

A high-performance wear-leveling algorithm for flash memory system. - Ching-Che Chung; Duo Sheng; Ning-Mi Hsueh (IEICE Electron. Express, 2012)

An All-Digital Large-N Audio Frequency Synthesizer for HDMI Applications. - Ching-Che Chung; Duo Sheng; Chia-Lin Chang; Wei-Da Ho; Yang-Di Lin; Fang-Nien Lu (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Low-Power DCO Using Interlaced Hysteresis Delay Cells. - Chien-Ying Yu; Ching-Che Chung; Chia-Jung Yu; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A high-resolution and one-cycle conversion time-to-digital converter architecture for PET image applications. - Duo Sheng; Ching-Che Chung; Chih-Chung Huang; Jia-Wei Jian (EMBC, 2013)

An all-digital on-chip silicon oscillator with automatic VT range selection relative modeling. - Ching-Che Chung; Jhih-Wei Li (ISCAS, 2013)

A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance. - Ching-Che Chung; Chang-Jun Li (VLSI-DAT, 2013)

A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices. - Ching-Che Chung; Duo Sheng; Wei-Siang Su (VLSI-DAT, 2013)

A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS. - Ching-Che Chung; Duo Sheng; Wei-Da Ho (IEICE Electron. Express, 2013)

An all-digital on-chip abnormal temperature warning sensor for dynamic thermal management. - Ching-Che Chung; Jhih-Wei Li (SoCC, 2014)

All-digital delay-locked loop for 3D-IC die-to-die clock synchronization. - Ching-Che Chung; Chi-Yu Hou (VLSI-DAT, 2014)

An all-digital phase-locked loop compiler with liberty timing files. - Ching-Che Chung; Duo Sheng; Chen-Han Chen (VLSI-DAT, 2014)

High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications. - Duo Sheng; Ching-Che Chung; Hsiu-Fan Lai; Shu-Syun Jhao (IEICE Electron. Express, 2014)

Partial Parity Cache and Data Cache Management Method to Improve the Performance of an SSD-Based RAID. - Ching-Che Chung; Hao-Hsiang Hsu (IEEE Trans. Very Large Scale Integr. Syst., 2014)

High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology. - Ching-Che Chung; Duo Sheng; Sung-En Shen (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 1 Mb/s-40 Mb/s human body channel communication transceiver. - Ching-Che Chung; Chi-Tung Chang; Chih-Yu Lin (VLSI-DAT, 2015)

A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator. - Ching-Che Chung; Duo Sheng; Wei-Da Ho (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector. - Ching-Che Chung; Duo Sheng; Chang-Jun Li (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An all-digital voltage sensor for static voltage drop measurements. - Ching-Che Chung; Mei-I Sun (SAS, 2016)

A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology. - Ching-Che Chung; Chi-Kuang Lo (IEICE Electron. Express, 2016)

A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling. - Ching-Che Chung; Wei-Siang Su; Chi-Kuang Lo (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A reference-less all-digital transceiver for human body channel communication. - Ching-Che Chung; Yi-Che Tsai; Ming-Chieh Li (VLSI-DAT, 2017)

A cell-based 5-MHz on-chip clock generator. - Ching-Che Chung; Jhih-Wei Li (Turkish J. Electr. Eng. Comput. Sci., 2017)

An area-efficient and wide-range digital DLL for per-pin deskew applications. - Ching-Che Chung; Chien-Ying Yu (Turkish J. Electr. Eng. Comput. Sci., 2017)

An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications. - Ching-Che Chung; Chi-Yu Hou (Microelectron. J., 2017)

Built-in Self-Test Circuits for All-digital Phase-Locked Loops. - Ching-Che Chung; Wei-Jung Chu; Yi-Ting Tsai (ICCE-TW, 2019)

Design of a DBN Hardware Accelerator for Handwritten Digit Recognitions. - Ching-Che Chung; Yi-Zeng Lee; Huai-Xiang Zhang (ICCE-TW, 2019)

An All-Digital Temperature Sensor with Process and Voltage Variation Tolerance for IoT Applications. - Ching-Che Chung; Hsin-Han Huang (SoCC, 2019)

A fast phase tracking reference-less all-digital CDR circuit for human body channel communication. - Ching-Che Chung; Duo Sheng; Ming-Chieh Li; Yi-Che Tsai (Microelectron. J., 2019)

A DBN Hardware Accelerator for Auditory Scene Classification. - Ching-Che Chung; Huai-Xiang Zhang; Ming-You Hung; Hong-Jin Jian (ICCE-TW, 2020)

Design of a human body channel communication transceiver using convolutional codes. - Ching-Che Chung; Duo Sheng; Ming-Hsuan Li (Microelectron. J., 2020)

A Body Channel Communication Transceiver with a 16x Oversampling CDR and Convolutional Codes. - Ching-Che Chung; Yi-Ting Tsai (VLSI-DAT, 2022)

A Maximum Logarithmic Maximum a Posteriori Probability Based Soft-Input Soft-Output Detector for the Coded Spatial Modulation Systems. - Tsung-Hsien Liu; Ting-Xu Jiang; Ching-Che Chung; Yuan-Sun Chu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Lightweight CNN hardware accelerator using the ternary quantization method for fault diagnosis of CNC machinery. - Ching-Che Chung; Yu-Pei Liang; Jo-Chen Huang (ICCE-Taiwan, 2023)

CNN Hardware Accelerator for Real-Time Bearing Fault Diagnosis. - Ching-Che Chung; Yu-Pei Liang; Hong-Jin Jiang (Sensors, 2023)

A Multiplier-Free Convolution Neural Network Hardware Accelerator for Real-Time Bearing Condition Detection of CNC Machinery. - Yu-Pei Liang; Ming-You Hung; Ching-Che Chung (Sensors, 2023)

A Low-Power Hierarchical CNN Hardware Accelerator for Bearing Fault Diagnosis. - Yu-Pei Liang; Yao-Shun Hsu; Ching-Che Chung (IEEE Trans. Instrum. Meas., 2024)

Implementation of Lightweight Convolutional Neural Networks with an Early Exit Mechanism Utilizing 40 nm CMOS Process for Fire Detection in Unmanned Aerial Vehicles. - Yu-Pei Liang; Chen-Ming Chang; Ching-Che Chung (Sensors, 2024)