Time-Zone: A New Algorithm for Register Allocation in Data Path Synthesis. - Ching-Chuen Jong; Y. Y. H. Lam; S. S. Lim; T. S. Teng (ISCAS, 1994)

FPGA implementation of a digital IQ demodulator using VHDL. - Ching-Chuen Jong; Y. Y. H. Lam; L. S. Ng (FPL, 1997)

A lower bound on general minimal resource interval scheduling with arbitrary component selection. - Z. X. Shen; Ching-Chuen Jong (ISCAS (6), 1999)

Functional area lower bound and upper bound on multicomponentselection for interval scheduling. - Zhaoxuan Shen; Ching-Chuen Jong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Lower Bound Estimation of Hardware Resources for Scheduling in High-Level Synthesis. - Zhaoxuan Shen; Jong Ching Chuen (J. Comput. Sci. Technol., 2002)

Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs. - Luo Jianwen; Jong Ching Chuen (DSD, 2004)

Efficient algorithms for common subexpression elimination in digital filter design. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (ICASSP (5), 2004)

HWP: a new insight into canonical signed digit. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (ISCAS (5), 2004)

A new contention resolution algorithm for the design of minimal logic depth multiplierless filters. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (ISCAS (3), 2004)

Using symbolic computer algebra for subexpression factorization and subexpression decomposition in high level synthesis. - Xianwu Xing; Ching-Chuen Jong (ISCAS (6), 2005)

I2CRA: contention resolution algorithm for intra- and inter-coefficient common subexpression elimination. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (ISCAS (2), 2005)

Contention resolution algorithm for common subexpression elimination in digital filter design. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Matrix Inversion on Reconfigurable Hardware using Binary-coded z-path CORDIC. - Luo Jianwen; Jong Ching Chuen (APCCAS, 2006)

A new integrated approach to the design of low-complexity FIR filters. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (ISCAS, 2006)

Hamming weight pyramid - A new insight into canonical signed digit representation and its applications. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (Comput. Electr. Eng., 2007)

A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesis. - Xianwu Xing; Ching-Chuen Jong (Microelectron. J., 2007)

Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

High-speed and low-power serial accumulator for serial/parallel multiplier. - Manas Ranjan Meher; Ching-Chuen Jong; Chip-Hong Chang (APCCAS, 2008)

A low complexity modulo 2n+1 squarer design. - Ramya Muralidharan; Chip-Hong Chang; Ching-Chuen Jong (APCCAS, 2008)

Contention Resolution - A New Approach to Versatile Subexpressions Sharing in Multiple Constant Multiplications. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Time-multiplexed Data Flow Graph for the Design of Configurable Multiplier Block. - Jiajia Chen 002; Chip-Hong Chang; Ching-Chuen Jong (ISCAS, 2009)

Multivoltage Multifrequency Low-Energy Synthesis for Functionally Pipelined Datapath. - Xianwu Xing; Ching-Chuen Jong (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Floorplan-Driven Multivoltage High-Level Synthesis. - Xianwu Xing; Ching-Chuen Jong (VLSI Design, 2009)

High accuracy binary logarithmic conversion using range mapping for DSP applications. - Joshua Yung Lih Low; Ching-Chuen Jong (APCCAS, 2010)

A novel counter-based low complexity inner-product architecture for high speed inputs. - Manas Ranjan Meher; Ching-Chuen Jong; Chip-Hong Chang; Jeremy Yung Shern Low (ISCAS, 2010)

A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters. - Manas Ranjan Meher; Ching-Chuen Jong; Chip-Hong Chang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. - Howard Tang; Joshua Yung Lih Low; Jeremy Yung Shern Low; Liter Siek; Ching-Chuen Jong; Chip-Hong Chang (APCCAS, 2012)

A fast and compact circuit for integer square root computation based on Mitchell logarithmic method. - Joshua Yung Lih Low; Ching-Chuen Jong; Jeremy Yung Shern Low; Thian Fatt Tay; Chip-Hong Chang (ISCAS, 2012)

Scalable linear array architectures for matrix inversion using Bi-z CORDIC. - J. W. Luo; Ching-Chuen Jong (Microelectron. J., 2012)

An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture. - Manas Ranjan Meher; Ching-Chuen Jong; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Non-iterative high speed division computation based on Mitchell logarithmic method. - Joshua Yung Lih Low; Ching-Chuen Jong (ISCAS, 2013)

A Memory-Efficient Tables-and-Additions Method for Accurate Computation of Elementary Functions. - Joshua Yung Lih Low; Ching-Chuen Jong (IEEE Trans. Computers, 2013)

A Memory-Efficient Scalable Architecture for Lifting-Based Discrete Wavelet Transform. - Yusong Hu; Ching-Chuen Jong (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Memory-Efficient High-Throughput Architecture for Lifting-Based Multi-Level 2-D DWT. - Yusong Hu; Ching-Chuen Jong (IEEE Trans. Signal Process., 2013)

Apps-usage driven energy management for multicore mobile computing systems. - Hou Zhao Qi Rex; Jong Ching Chuen; Andreas Herkersdorf (ISIC, 2014)

Memory-efficient discrete wavelet transform architecture based on wordlength optimization. - Yusong Hu; Ching-Chuen Jong (ISCAS, 2015)

A curve fitting approach for non-iterative divider design with accuracy and performance trade-off. - Lei Wu; Ching-Chuen Jong (NEWCAS, 2015)

Unified Mitchell-Based Approximation for Efficient Logarithmic Conversion Circuit. - Joshua Yung Lih Low; Ching-Chuen Jong (IEEE Trans. Computers, 2015)

Linux apps-usage-driven power dissipation-aware scheduler. - Hou Zhao Qi Rex; Jong Ching Chuen; Andreas Herkersdorf (ISCAS, 2016)

A VLSI architecture for real-time gradient guided image filtering. - Lei Wu; Ching-Chuen Jong (VLSI-SoC, 2016)

ANN Predicted Apps-Usage Aware Linux Scheduler for Asymmetrical Multi Cluster SoC. - Hou Zhao Qi Rex; Jong Ching Chuen; Andreas Herkersdorf (J. Softw., 2016)

Range Mapping - A Fresh Approach to High Accuracy Mitchell-Based Logarithmic Conversion Circuit Design. - Joshua Yung Lih Low; Ching-Chuen Jong (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A High-Throughput VLSI Architecture for Real-Time Full-HD Gradient Guided Image Filter. - Lei Wu; Ching-Chuen Jong (IEEE Trans. Circuits Syst. Video Technol., 2019)

Non-iterative division circuit design with accuracy and performance trade-off based on mixed integer linear programming approach. - Lei Wu; Ching-Chuen Jong (Microelectron. J., 2022)